1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 2; RUN: opt -loop-reduce -S %s | FileCheck %s 3 4target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" 5target triple = "x86_64-apple-macos" 6 7declare i1 @cond() 8 9define ptr @test(ptr %dst, i64 %v4, i64 %v5, i64 %v6, i64 %v7) { 10; CHECK-LABEL: define ptr @test 11; CHECK-SAME: (ptr [[DST:%.*]], i64 [[V4:%.*]], i64 [[V5:%.*]], i64 [[V6:%.*]], i64 [[V7:%.*]]) { 12; CHECK-NEXT: entry: 13; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[V5]], [[V4]] 14; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[TMP0]], 4 15; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[V7]], [[V6]] 16; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 3 17; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], -8 18; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP4]] 19; CHECK-NEXT: [[TMP5:%.*]] = shl nsw i64 [[V5]], 3 20; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP5]], 8 21; CHECK-NEXT: [[TMP7:%.*]] = shl i64 [[V4]], 4 22; CHECK-NEXT: [[TMP8:%.*]] = add nuw nsw i64 [[TMP7]], 8 23; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[V5]], [[TMP8]] 24; CHECK-NEXT: [[TMP10:%.*]] = shl i64 [[V7]], 3 25; CHECK-NEXT: [[TMP11:%.*]] = shl i64 [[V6]], 3 26; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP10]], [[TMP11]] 27; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], -8 28; CHECK-NEXT: [[SCEVGEP3:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP13]] 29; CHECK-NEXT: br label [[LOOP:%.*]] 30; CHECK: loop: 31; CHECK-NEXT: [[LSR_IV4:%.*]] = phi ptr [ [[SCEVGEP5:%.*]], [[LOOP]] ], [ [[SCEVGEP3]], [[ENTRY:%.*]] ] 32; CHECK-NEXT: [[LSR_IV:%.*]] = phi ptr [ [[SCEVGEP1:%.*]], [[LOOP]] ], [ [[SCEVGEP]], [[ENTRY]] ] 33; CHECK-NEXT: [[SCEVGEP6:%.*]] = getelementptr i8, ptr [[LSR_IV4]], i64 [[TMP9]] 34; CHECK-NEXT: store i64 0, ptr [[SCEVGEP6]], align 8 35; CHECK-NEXT: [[C:%.*]] = call i1 @cond() 36; CHECK-NEXT: [[SCEVGEP1]] = getelementptr i8, ptr [[LSR_IV]], i64 [[TMP6]] 37; CHECK-NEXT: [[SCEVGEP2:%.*]] = getelementptr i8, ptr [[SCEVGEP1]], i64 [[TMP1]] 38; CHECK-NEXT: [[SCEVGEP5]] = getelementptr i8, ptr [[LSR_IV4]], i64 [[TMP6]] 39; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[LOOP]] 40; CHECK: exit: 41; CHECK-NEXT: [[RES:%.*]] = phi ptr [ [[SCEVGEP2]], [[LOOP]] ] 42; CHECK-NEXT: ret ptr [[RES]] 43; 44entry: 45 %mul = mul nsw i64 %v5, %v4 46 %add.ptr162 = getelementptr inbounds i64, ptr %dst, i64 %v6 47 %add.ptr164 = getelementptr inbounds i64, ptr %add.ptr162, i64 %mul 48 %add.ptr166 = getelementptr inbounds i64, ptr %add.ptr164, i64 %v7 49 %add.ptr167 = getelementptr inbounds i64, ptr %add.ptr166, i64 -1 50 %add.ptr249 = getelementptr inbounds i64, ptr %add.ptr167, i64 %mul 51 br label %loop 52 53loop: 54 %iv = phi ptr [ %add.ptr249, %entry ], [ %iv.next, %loop ] 55 %gep.iv.1 = getelementptr inbounds i64, ptr %iv, i64 %v5 56 store i64 0, ptr %gep.iv.1, align 8 57 %iv.next = getelementptr inbounds i64, ptr %gep.iv.1, i64 1 58 %c = call i1 @cond() 59 br i1 %c, label %exit, label %loop 60 61exit: 62 %res = phi ptr [ %iv.next, %loop ] 63 ret ptr %res 64} 65 66define i32 @test_pr63678(i1 %c) { 67; CHECK-LABEL: define i32 @test_pr63678 68; CHECK-SAME: (i1 [[C:%.*]]) { 69; CHECK-NEXT: entry: 70; CHECK-NEXT: br label [[LOOP_1_PREHEADER:%.*]] 71; CHECK: bb: 72; CHECK-NEXT: [[TOBOOL1_NOT:%.*]] = icmp eq i32 [[LSR_IV_NEXT66:%.*]], 0 73; CHECK-NEXT: br label [[LOOP_1_PREHEADER]] 74; CHECK: loop.1.preheader: 75; CHECK-NEXT: [[IV_PH:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 1, [[BB:%.*]] ] 76; CHECK-NEXT: [[TMP0:%.*]] = sub i32 1, [[IV_PH]] 77; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[TMP0]], -1 78; CHECK-NEXT: br label [[LOOP_1:%.*]] 79; CHECK: loop.1: 80; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[TMP1]], [[LOOP_1_PREHEADER]] ], [ [[LSR_IV_NEXT:%.*]], [[LOOP_1]] ] 81; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], -1 82; CHECK-NEXT: br i1 false, label [[LOOP_1_LOOP_2_CRIT_EDGE:%.*]], label [[LOOP_1]] 83; CHECK: loop.1.loop.2_crit_edge: 84; CHECK-NEXT: br label [[LOOP_2:%.*]] 85; CHECK: loop.2: 86; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[LOOP_2]] ], [ [[LSR_IV]], [[LOOP_1_LOOP_2_CRIT_EDGE]] ] 87; CHECK-NEXT: [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], -1 88; CHECK-NEXT: br i1 false, label [[LOOP_3_PREHEADER:%.*]], label [[LOOP_2]] 89; CHECK: loop.3.preheader: 90; CHECK-NEXT: br label [[LOOP_3:%.*]] 91; CHECK: loop.3: 92; CHECK-NEXT: [[LSR_IV3:%.*]] = phi i32 [ [[LSR_IV1]], [[LOOP_3_PREHEADER]] ], [ [[LSR_IV_NEXT4:%.*]], [[LOOP_3]] ] 93; CHECK-NEXT: [[LSR_IV_NEXT4]] = add i32 [[LSR_IV3]], -1 94; CHECK-NEXT: br i1 false, label [[LOOP_4_PREHEADER:%.*]], label [[LOOP_3]] 95; CHECK: loop.4.preheader: 96; CHECK-NEXT: br label [[LOOP_4:%.*]] 97; CHECK: loop.4: 98; CHECK-NEXT: [[LSR_IV5:%.*]] = phi i32 [ [[LSR_IV3]], [[LOOP_4_PREHEADER]] ], [ [[LSR_IV_NEXT6:%.*]], [[LOOP_4]] ] 99; CHECK-NEXT: [[LSR_IV_NEXT6]] = add i32 [[LSR_IV5]], -1 100; CHECK-NEXT: br i1 false, label [[LOOP_5_PREHEADER:%.*]], label [[LOOP_4]] 101; CHECK: loop.5.preheader: 102; CHECK-NEXT: br label [[LOOP_5:%.*]] 103; CHECK: loop.5: 104; CHECK-NEXT: [[LSR_IV7:%.*]] = phi i32 [ [[LSR_IV5]], [[LOOP_5_PREHEADER]] ], [ [[LSR_IV_NEXT8:%.*]], [[LOOP_5]] ] 105; CHECK-NEXT: [[LSR_IV_NEXT8]] = add i32 [[LSR_IV7]], -1 106; CHECK-NEXT: br i1 false, label [[LOOP_6_PREHEADER:%.*]], label [[LOOP_5]] 107; CHECK: loop.6.preheader: 108; CHECK-NEXT: br label [[LOOP_6:%.*]] 109; CHECK: loop.6: 110; CHECK-NEXT: [[LSR_IV9:%.*]] = phi i32 [ [[LSR_IV7]], [[LOOP_6_PREHEADER]] ], [ [[LSR_IV_NEXT10:%.*]], [[LOOP_6]] ] 111; CHECK-NEXT: [[LSR_IV_NEXT10]] = add i32 [[LSR_IV9]], -1 112; CHECK-NEXT: br i1 false, label [[LOOP_135_PREHEADER:%.*]], label [[LOOP_6]] 113; CHECK: loop.135.preheader: 114; CHECK-NEXT: br label [[LOOP_135:%.*]] 115; CHECK: loop.135: 116; CHECK-NEXT: [[LSR_IV11:%.*]] = phi i32 [ [[LSR_IV9]], [[LOOP_135_PREHEADER]] ], [ [[LSR_IV_NEXT12:%.*]], [[LOOP_135]] ] 117; CHECK-NEXT: [[LSR_IV_NEXT12]] = add i32 [[LSR_IV11]], -1 118; CHECK-NEXT: br i1 false, label [[LOOP_1_1_PREHEADER:%.*]], label [[LOOP_135]] 119; CHECK: loop.1.1.preheader: 120; CHECK-NEXT: br label [[LOOP_1_1:%.*]] 121; CHECK: loop.1.1: 122; CHECK-NEXT: [[LSR_IV13:%.*]] = phi i32 [ [[LSR_IV11]], [[LOOP_1_1_PREHEADER]] ], [ [[LSR_IV_NEXT14:%.*]], [[LOOP_1_1]] ] 123; CHECK-NEXT: [[LSR_IV_NEXT14]] = add i32 [[LSR_IV13]], -1 124; CHECK-NEXT: br i1 false, label [[LOOP_2_1_PREHEADER:%.*]], label [[LOOP_1_1]] 125; CHECK: loop.2.1.preheader: 126; CHECK-NEXT: br label [[LOOP_2_1:%.*]] 127; CHECK: loop.2.1: 128; CHECK-NEXT: [[LSR_IV15:%.*]] = phi i32 [ [[LSR_IV13]], [[LOOP_2_1_PREHEADER]] ], [ [[LSR_IV_NEXT16:%.*]], [[LOOP_2_1]] ] 129; CHECK-NEXT: [[LSR_IV_NEXT16]] = add i32 [[LSR_IV15]], -1 130; CHECK-NEXT: br i1 false, label [[LOOP_3_1_PREHEADER:%.*]], label [[LOOP_2_1]] 131; CHECK: loop.3.1.preheader: 132; CHECK-NEXT: br label [[LOOP_3_1:%.*]] 133; CHECK: loop.3.1: 134; CHECK-NEXT: [[LSR_IV17:%.*]] = phi i32 [ [[LSR_IV15]], [[LOOP_3_1_PREHEADER]] ], [ [[LSR_IV_NEXT18:%.*]], [[LOOP_3_1]] ] 135; CHECK-NEXT: [[LSR_IV_NEXT18]] = add i32 [[LSR_IV17]], -1 136; CHECK-NEXT: br i1 false, label [[LOOP_4_1_PREHEADER:%.*]], label [[LOOP_3_1]] 137; CHECK: loop.4.1.preheader: 138; CHECK-NEXT: br label [[LOOP_4_1:%.*]] 139; CHECK: loop.4.1: 140; CHECK-NEXT: [[LSR_IV19:%.*]] = phi i32 [ [[LSR_IV17]], [[LOOP_4_1_PREHEADER]] ], [ [[LSR_IV_NEXT20:%.*]], [[LOOP_4_1]] ] 141; CHECK-NEXT: [[LSR_IV_NEXT20]] = add i32 [[LSR_IV19]], -1 142; CHECK-NEXT: br i1 false, label [[LOOP_5_1_PREHEADER:%.*]], label [[LOOP_4_1]] 143; CHECK: loop.5.1.preheader: 144; CHECK-NEXT: br label [[LOOP_5_1:%.*]] 145; CHECK: loop.5.1: 146; CHECK-NEXT: [[LSR_IV21:%.*]] = phi i32 [ [[LSR_IV19]], [[LOOP_5_1_PREHEADER]] ], [ [[LSR_IV_NEXT22:%.*]], [[LOOP_5_1]] ] 147; CHECK-NEXT: [[LSR_IV_NEXT22]] = add i32 [[LSR_IV21]], -1 148; CHECK-NEXT: br i1 false, label [[LOOP_6_1_PREHEADER:%.*]], label [[LOOP_5_1]] 149; CHECK: loop.6.1.preheader: 150; CHECK-NEXT: br label [[LOOP_6_1:%.*]] 151; CHECK: loop.6.1: 152; CHECK-NEXT: [[LSR_IV23:%.*]] = phi i32 [ [[LSR_IV21]], [[LOOP_6_1_PREHEADER]] ], [ [[LSR_IV_NEXT24:%.*]], [[LOOP_6_1]] ] 153; CHECK-NEXT: [[LSR_IV_NEXT24]] = add i32 [[LSR_IV23]], -1 154; CHECK-NEXT: br i1 false, label [[LOOP_241_PREHEADER:%.*]], label [[LOOP_6_1]] 155; CHECK: loop.241.preheader: 156; CHECK-NEXT: br label [[LOOP_241:%.*]] 157; CHECK: loop.241: 158; CHECK-NEXT: [[LSR_IV25:%.*]] = phi i32 [ [[LSR_IV23]], [[LOOP_241_PREHEADER]] ], [ [[LSR_IV_NEXT26:%.*]], [[LOOP_241]] ] 159; CHECK-NEXT: [[LSR_IV_NEXT26]] = add i32 [[LSR_IV25]], -1 160; CHECK-NEXT: br i1 false, label [[LOOP_1_2_PREHEADER:%.*]], label [[LOOP_241]] 161; CHECK: loop.1.2.preheader: 162; CHECK-NEXT: br label [[LOOP_1_2:%.*]] 163; CHECK: loop.1.2: 164; CHECK-NEXT: [[LSR_IV27:%.*]] = phi i32 [ [[LSR_IV25]], [[LOOP_1_2_PREHEADER]] ], [ [[LSR_IV_NEXT28:%.*]], [[LOOP_1_2]] ] 165; CHECK-NEXT: [[LSR_IV_NEXT28]] = add i32 [[LSR_IV27]], -1 166; CHECK-NEXT: br i1 false, label [[LOOP_2_2_PREHEADER:%.*]], label [[LOOP_1_2]] 167; CHECK: loop.2.2.preheader: 168; CHECK-NEXT: br label [[LOOP_2_2:%.*]] 169; CHECK: loop.2.2: 170; CHECK-NEXT: [[LSR_IV29:%.*]] = phi i32 [ [[LSR_IV27]], [[LOOP_2_2_PREHEADER]] ], [ [[LSR_IV_NEXT30:%.*]], [[LOOP_2_2]] ] 171; CHECK-NEXT: [[LSR_IV_NEXT30]] = add i32 [[LSR_IV29]], -1 172; CHECK-NEXT: br i1 false, label [[LOOP_3_2_PREHEADER:%.*]], label [[LOOP_2_2]] 173; CHECK: loop.3.2.preheader: 174; CHECK-NEXT: br label [[LOOP_3_2:%.*]] 175; CHECK: loop.3.2: 176; CHECK-NEXT: [[LSR_IV31:%.*]] = phi i32 [ [[LSR_IV29]], [[LOOP_3_2_PREHEADER]] ], [ [[LSR_IV_NEXT32:%.*]], [[LOOP_3_2]] ] 177; CHECK-NEXT: [[LSR_IV_NEXT32]] = add i32 [[LSR_IV31]], -1 178; CHECK-NEXT: br i1 false, label [[LOOP_4_2_PREHEADER:%.*]], label [[LOOP_3_2]] 179; CHECK: loop.4.2.preheader: 180; CHECK-NEXT: br label [[LOOP_4_2:%.*]] 181; CHECK: loop.4.2: 182; CHECK-NEXT: [[LSR_IV33:%.*]] = phi i32 [ [[LSR_IV31]], [[LOOP_4_2_PREHEADER]] ], [ [[LSR_IV_NEXT34:%.*]], [[LOOP_4_2]] ] 183; CHECK-NEXT: [[LSR_IV_NEXT34]] = add i32 [[LSR_IV33]], -1 184; CHECK-NEXT: br i1 false, label [[LOOP_5_2_PREHEADER:%.*]], label [[LOOP_4_2]] 185; CHECK: loop.5.2.preheader: 186; CHECK-NEXT: br label [[LOOP_5_2:%.*]] 187; CHECK: loop.5.2: 188; CHECK-NEXT: [[LSR_IV35:%.*]] = phi i32 [ [[LSR_IV33]], [[LOOP_5_2_PREHEADER]] ], [ [[LSR_IV_NEXT36:%.*]], [[LOOP_5_2]] ] 189; CHECK-NEXT: [[LSR_IV_NEXT36]] = add i32 [[LSR_IV35]], -1 190; CHECK-NEXT: br i1 false, label [[LOOP_6_2_PREHEADER:%.*]], label [[LOOP_5_2]] 191; CHECK: loop.6.2.preheader: 192; CHECK-NEXT: br label [[LOOP_6_2:%.*]] 193; CHECK: loop.6.2: 194; CHECK-NEXT: [[LSR_IV37:%.*]] = phi i32 [ [[LSR_IV35]], [[LOOP_6_2_PREHEADER]] ], [ [[LSR_IV_NEXT38:%.*]], [[LOOP_6_2]] ] 195; CHECK-NEXT: [[LSR_IV_NEXT38]] = add i32 [[LSR_IV37]], -1 196; CHECK-NEXT: br i1 false, label [[LOOP_347_PREHEADER:%.*]], label [[LOOP_6_2]] 197; CHECK: loop.347.preheader: 198; CHECK-NEXT: br label [[LOOP_347:%.*]] 199; CHECK: loop.347: 200; CHECK-NEXT: [[LSR_IV39:%.*]] = phi i32 [ [[LSR_IV37]], [[LOOP_347_PREHEADER]] ], [ [[LSR_IV_NEXT40:%.*]], [[LOOP_347]] ] 201; CHECK-NEXT: [[LSR_IV_NEXT40]] = add i32 [[LSR_IV39]], -1 202; CHECK-NEXT: br i1 false, label [[LOOP_1_3_PREHEADER:%.*]], label [[LOOP_347]] 203; CHECK: loop.1.3.preheader: 204; CHECK-NEXT: br label [[LOOP_1_3:%.*]] 205; CHECK: loop.1.3: 206; CHECK-NEXT: [[LSR_IV41:%.*]] = phi i32 [ [[LSR_IV39]], [[LOOP_1_3_PREHEADER]] ], [ [[LSR_IV_NEXT42:%.*]], [[LOOP_1_3]] ] 207; CHECK-NEXT: [[LSR_IV_NEXT42]] = add i32 [[LSR_IV41]], -1 208; CHECK-NEXT: br i1 false, label [[LOOP_2_3_PREHEADER:%.*]], label [[LOOP_1_3]] 209; CHECK: loop.2.3.preheader: 210; CHECK-NEXT: br label [[LOOP_2_3:%.*]] 211; CHECK: loop.2.3: 212; CHECK-NEXT: [[LSR_IV43:%.*]] = phi i32 [ [[LSR_IV41]], [[LOOP_2_3_PREHEADER]] ], [ [[LSR_IV_NEXT44:%.*]], [[LOOP_2_3]] ] 213; CHECK-NEXT: [[LSR_IV_NEXT44]] = add i32 [[LSR_IV43]], -1 214; CHECK-NEXT: br i1 false, label [[LOOP_3_3_PREHEADER:%.*]], label [[LOOP_2_3]] 215; CHECK: loop.3.3.preheader: 216; CHECK-NEXT: br label [[LOOP_3_3:%.*]] 217; CHECK: loop.3.3: 218; CHECK-NEXT: [[LSR_IV45:%.*]] = phi i32 [ [[LSR_IV43]], [[LOOP_3_3_PREHEADER]] ], [ [[LSR_IV_NEXT46:%.*]], [[LOOP_3_3]] ] 219; CHECK-NEXT: [[LSR_IV_NEXT46]] = add i32 [[LSR_IV45]], -1 220; CHECK-NEXT: br i1 false, label [[LOOP_4_3_PREHEADER:%.*]], label [[LOOP_3_3]] 221; CHECK: loop.4.3.preheader: 222; CHECK-NEXT: br label [[LOOP_4_3:%.*]] 223; CHECK: loop.4.3: 224; CHECK-NEXT: [[LSR_IV47:%.*]] = phi i32 [ [[LSR_IV45]], [[LOOP_4_3_PREHEADER]] ], [ [[LSR_IV_NEXT48:%.*]], [[LOOP_4_3]] ] 225; CHECK-NEXT: [[LSR_IV_NEXT48]] = add i32 [[LSR_IV47]], -1 226; CHECK-NEXT: br i1 false, label [[LOOP_5_3_PREHEADER:%.*]], label [[LOOP_4_3]] 227; CHECK: loop.5.3.preheader: 228; CHECK-NEXT: br label [[LOOP_5_3:%.*]] 229; CHECK: loop.5.3: 230; CHECK-NEXT: [[LSR_IV49:%.*]] = phi i32 [ [[LSR_IV47]], [[LOOP_5_3_PREHEADER]] ], [ [[LSR_IV_NEXT50:%.*]], [[LOOP_5_3]] ] 231; CHECK-NEXT: [[LSR_IV_NEXT50]] = add i32 [[LSR_IV49]], -1 232; CHECK-NEXT: br i1 false, label [[LOOP_6_3_PREHEADER:%.*]], label [[LOOP_5_3]] 233; CHECK: loop.6.3.preheader: 234; CHECK-NEXT: br label [[LOOP_6_3:%.*]] 235; CHECK: loop.6.3: 236; CHECK-NEXT: [[LSR_IV51:%.*]] = phi i32 [ [[LSR_IV49]], [[LOOP_6_3_PREHEADER]] ], [ [[LSR_IV_NEXT52:%.*]], [[LOOP_6_3]] ] 237; CHECK-NEXT: [[LSR_IV_NEXT52]] = add i32 [[LSR_IV51]], -1 238; CHECK-NEXT: br i1 false, label [[LOOP_453_PREHEADER:%.*]], label [[LOOP_6_3]] 239; CHECK: loop.453.preheader: 240; CHECK-NEXT: br label [[LOOP_453:%.*]] 241; CHECK: loop.453: 242; CHECK-NEXT: [[LSR_IV53:%.*]] = phi i32 [ [[LSR_IV51]], [[LOOP_453_PREHEADER]] ], [ [[LSR_IV_NEXT54:%.*]], [[LOOP_453]] ] 243; CHECK-NEXT: [[LSR_IV_NEXT54]] = add i32 [[LSR_IV53]], -1 244; CHECK-NEXT: br i1 false, label [[LOOP_1_4_PREHEADER:%.*]], label [[LOOP_453]] 245; CHECK: loop.1.4.preheader: 246; CHECK-NEXT: br label [[LOOP_1_4:%.*]] 247; CHECK: loop.1.4: 248; CHECK-NEXT: [[LSR_IV55:%.*]] = phi i32 [ [[LSR_IV53]], [[LOOP_1_4_PREHEADER]] ], [ [[LSR_IV_NEXT56:%.*]], [[LOOP_1_4]] ] 249; CHECK-NEXT: [[LSR_IV_NEXT56]] = add i32 [[LSR_IV55]], -1 250; CHECK-NEXT: br i1 false, label [[LOOP_2_4_PREHEADER:%.*]], label [[LOOP_1_4]] 251; CHECK: loop.2.4.preheader: 252; CHECK-NEXT: br label [[LOOP_2_4:%.*]] 253; CHECK: loop.2.4: 254; CHECK-NEXT: [[LSR_IV57:%.*]] = phi i32 [ [[LSR_IV55]], [[LOOP_2_4_PREHEADER]] ], [ [[LSR_IV_NEXT58:%.*]], [[LOOP_2_4]] ] 255; CHECK-NEXT: [[LSR_IV_NEXT58]] = add i32 [[LSR_IV57]], -1 256; CHECK-NEXT: br i1 false, label [[LOOP_3_4_PREHEADER:%.*]], label [[LOOP_2_4]] 257; CHECK: loop.3.4.preheader: 258; CHECK-NEXT: br label [[LOOP_3_4:%.*]] 259; CHECK: loop.3.4: 260; CHECK-NEXT: [[LSR_IV59:%.*]] = phi i32 [ [[LSR_IV57]], [[LOOP_3_4_PREHEADER]] ], [ [[LSR_IV_NEXT60:%.*]], [[LOOP_3_4]] ] 261; CHECK-NEXT: [[LSR_IV_NEXT60]] = add i32 [[LSR_IV59]], -1 262; CHECK-NEXT: br i1 false, label [[LOOP_4_4_PREHEADER:%.*]], label [[LOOP_3_4]] 263; CHECK: loop.4.4.preheader: 264; CHECK-NEXT: br label [[LOOP_4_4:%.*]] 265; CHECK: loop.4.4: 266; CHECK-NEXT: [[LSR_IV61:%.*]] = phi i32 [ [[LSR_IV59]], [[LOOP_4_4_PREHEADER]] ], [ [[LSR_IV_NEXT62:%.*]], [[LOOP_4_4]] ] 267; CHECK-NEXT: [[LSR_IV_NEXT62]] = add i32 [[LSR_IV61]], -1 268; CHECK-NEXT: br i1 false, label [[LOOP_5_4_PREHEADER:%.*]], label [[LOOP_4_4]] 269; CHECK: loop.5.4.preheader: 270; CHECK-NEXT: br label [[LOOP_5_4:%.*]] 271; CHECK: loop.5.4: 272; CHECK-NEXT: [[LSR_IV63:%.*]] = phi i32 [ [[LSR_IV61]], [[LOOP_5_4_PREHEADER]] ], [ [[LSR_IV_NEXT64:%.*]], [[LOOP_5_4]] ] 273; CHECK-NEXT: [[LSR_IV_NEXT64]] = add i32 [[LSR_IV63]], 1 274; CHECK-NEXT: br i1 false, label [[LOOP_6_4_PREHEADER:%.*]], label [[LOOP_5_4]] 275; CHECK: loop.6.4.preheader: 276; CHECK-NEXT: br label [[LOOP_6_4:%.*]] 277; CHECK: loop.6.4: 278; CHECK-NEXT: [[LSR_IV65:%.*]] = phi i32 [ [[LSR_IV63]], [[LOOP_6_4_PREHEADER]] ], [ [[LSR_IV_NEXT66]], [[LOOP_6_4]] ] 279; CHECK-NEXT: [[LSR_IV_NEXT66]] = add i32 [[LSR_IV65]], 1 280; CHECK-NEXT: br label [[LOOP_6_4]] 281; 282entry: 283 br label %loop.1 284 285bb: 286 %tobool1.not = icmp eq i32 %d.4.6.4, 0 287 br label %loop.1 288 289loop.1: 290 %iv = phi i32 [ %iv.next, %loop.1 ], [ 1, %bb ], [ 0, %entry ] 291 %iv.next = add i32 %iv, 1 292 br i1 false, label %loop.1.loop.2_crit_edge, label %loop.1 293 294loop.1.loop.2_crit_edge: 295 br label %loop.2 296 297loop.2: 298 %iv58 = phi i32 [ %iv.next59, %loop.2 ], [ %iv, %loop.1.loop.2_crit_edge ] 299 %iv.next59 = add i32 %iv58, 1 300 br i1 false, label %loop.3, label %loop.2 301 302loop.3: 303 %iv60 = phi i32 [ %iv.next61, %loop.3 ], [ %iv58, %loop.2 ] 304 %iv.next61 = add i32 %iv60, 1 305 br i1 false, label %loop.4, label %loop.3 306 307loop.4: 308 %iv62 = phi i32 [ %iv.next63, %loop.4 ], [ %iv60, %loop.3 ] 309 %iv.next63 = add i32 %iv62, 1 310 br i1 false, label %loop.5, label %loop.4 311 312loop.5: 313 %iv64 = phi i32 [ %iv.next65, %loop.5 ], [ %iv62, %loop.4 ] 314 %iv.next65 = add i32 %iv64, 1 315 br i1 false, label %loop.6, label %loop.5 316 317loop.6: 318 %iv66 = phi i32 [ %iv.next67, %loop.6 ], [ %iv64, %loop.5 ] 319 %iv.next67 = add i32 %iv66, 1 320 br i1 false, label %loop.135, label %loop.6 321 322loop.135: 323 %iv68 = phi i32 [ %iv.next69, %loop.135 ], [ %iv66, %loop.6 ] 324 %iv.next69 = add i32 %iv68, 1 325 br i1 false, label %loop.1.1, label %loop.135 326 327loop.1.1: 328 %iv70 = phi i32 [ %iv.next71, %loop.1.1 ], [ %iv68, %loop.135 ] 329 %iv.next71 = add i32 %iv70, 1 330 br i1 false, label %loop.2.1, label %loop.1.1 331 332loop.2.1: 333 %iv72 = phi i32 [ %iv.next73, %loop.2.1 ], [ %iv70, %loop.1.1 ] 334 %iv.next73 = add i32 %iv72, 1 335 br i1 false, label %loop.3.1, label %loop.2.1 336 337loop.3.1: 338 %iv74 = phi i32 [ %iv.next75, %loop.3.1 ], [ %iv72, %loop.2.1 ] 339 %iv.next75 = add i32 %iv74, 1 340 br i1 false, label %loop.4.1, label %loop.3.1 341 342loop.4.1: 343 %iv76 = phi i32 [ %iv.next77, %loop.4.1 ], [ %iv74, %loop.3.1 ] 344 %iv.next77 = add i32 %iv76, 1 345 br i1 false, label %loop.5.1, label %loop.4.1 346 347loop.5.1: 348 %iv78 = phi i32 [ %iv.next79, %loop.5.1 ], [ %iv76, %loop.4.1 ] 349 %iv.next79 = add i32 %iv78, 1 350 br i1 false, label %loop.6.1, label %loop.5.1 351 352loop.6.1: 353 %iv80 = phi i32 [ %iv.next81, %loop.6.1 ], [ %iv78, %loop.5.1 ] 354 %iv.next81 = add i32 %iv80, 1 355 br i1 false, label %loop.241, label %loop.6.1 356 357loop.241: 358 %iv82 = phi i32 [ %iv.next83, %loop.241 ], [ %iv80, %loop.6.1 ] 359 %iv.next83 = add i32 %iv82, 1 360 br i1 false, label %loop.1.2, label %loop.241 361 362loop.1.2: 363 %iv84 = phi i32 [ %iv.next85, %loop.1.2 ], [ %iv82, %loop.241 ] 364 %iv.next85 = add i32 %iv84, 1 365 br i1 false, label %loop.2.2, label %loop.1.2 366 367loop.2.2: 368 %iv86 = phi i32 [ %iv.next87, %loop.2.2 ], [ %iv84, %loop.1.2 ] 369 %iv.next87 = add i32 %iv86, 1 370 br i1 false, label %loop.3.2, label %loop.2.2 371 372loop.3.2: 373 %iv88 = phi i32 [ %iv.next89, %loop.3.2 ], [ %iv86, %loop.2.2 ] 374 %iv.next89 = add i32 %iv88, 1 375 br i1 false, label %loop.4.2, label %loop.3.2 376 377loop.4.2: 378 %iv90 = phi i32 [ %iv.next91, %loop.4.2 ], [ %iv88, %loop.3.2 ] 379 %iv.next91 = add i32 %iv90, 1 380 br i1 false, label %loop.5.2, label %loop.4.2 381 382loop.5.2: 383 %iv92 = phi i32 [ %iv.next93, %loop.5.2 ], [ %iv90, %loop.4.2 ] 384 %iv.next93 = add i32 %iv92, 1 385 br i1 false, label %loop.6.2, label %loop.5.2 386 387loop.6.2: 388 %iv94 = phi i32 [ %iv.next95, %loop.6.2 ], [ %iv92, %loop.5.2 ] 389 %iv.next95 = add i32 %iv94, 1 390 br i1 false, label %loop.347, label %loop.6.2 391 392loop.347: 393 %iv96 = phi i32 [ %iv.next97, %loop.347 ], [ %iv94, %loop.6.2 ] 394 %iv.next97 = add i32 %iv96, 1 395 br i1 false, label %loop.1.3, label %loop.347 396 397loop.1.3: 398 %iv98 = phi i32 [ %iv.next99, %loop.1.3 ], [ %iv96, %loop.347 ] 399 %iv.next99 = add i32 %iv98, 1 400 br i1 false, label %loop.2.3, label %loop.1.3 401 402loop.2.3: 403 %iv100 = phi i32 [ %iv.next101, %loop.2.3 ], [ %iv98, %loop.1.3 ] 404 %iv.next101 = add i32 %iv100, 1 405 br i1 false, label %loop.3.3, label %loop.2.3 406 407loop.3.3: 408 %iv102 = phi i32 [ %iv.next103, %loop.3.3 ], [ %iv100, %loop.2.3 ] 409 %iv.next103 = add i32 %iv102, 1 410 br i1 false, label %loop.4.3, label %loop.3.3 411 412loop.4.3: 413 %iv104 = phi i32 [ %iv.next105, %loop.4.3 ], [ %iv102, %loop.3.3 ] 414 %iv.next105 = add i32 %iv104, 1 415 br i1 false, label %loop.5.3, label %loop.4.3 416 417loop.5.3: 418 %iv106 = phi i32 [ %iv.next107, %loop.5.3 ], [ %iv104, %loop.4.3 ] 419 %iv.next107 = add i32 %iv106, 1 420 br i1 false, label %loop.6.3, label %loop.5.3 421 422loop.6.3: 423 %iv108 = phi i32 [ %iv.next109, %loop.6.3 ], [ %iv106, %loop.5.3 ] 424 %iv.next109 = add i32 %iv108, 1 425 br i1 false, label %loop.453, label %loop.6.3 426 427loop.453: 428 %iv110 = phi i32 [ %iv.next111, %loop.453 ], [ %iv108, %loop.6.3 ] 429 %iv.next111 = add i32 %iv110, 1 430 br i1 false, label %loop.1.4, label %loop.453 431 432loop.1.4: 433 %iv112 = phi i32 [ %iv.next113, %loop.1.4 ], [ %iv110, %loop.453 ] 434 %iv.next113 = add i32 %iv112, 1 435 br i1 false, label %loop.2.4, label %loop.1.4 436 437loop.2.4: 438 %iv114 = phi i32 [ %iv.next115, %loop.2.4 ], [ %iv112, %loop.1.4 ] 439 %iv.next115 = add i32 %iv114, 1 440 br i1 false, label %loop.3.4, label %loop.2.4 441 442loop.3.4: 443 %iv116 = phi i32 [ %iv.next117, %loop.3.4 ], [ %iv114, %loop.2.4 ] 444 %iv.next117 = add i32 %iv116, 1 445 br i1 false, label %loop.4.4, label %loop.3.4 446 447loop.4.4: 448 %iv118 = phi i32 [ %iv.next119, %loop.4.4 ], [ %iv116, %loop.3.4 ] 449 %iv.next119 = add i32 %iv118, 1 450 br i1 false, label %loop.5.4, label %loop.4.4 451 452loop.5.4: 453 %iv120 = phi i32 [ %iv.next121, %loop.5.4 ], [ %iv118, %loop.4.4 ] 454 %iv.next121 = add i32 %iv120, -1 455 br i1 false, label %loop.6.4, label %loop.5.4 456 457loop.6.4: 458 %d.4.6.4 = phi i32 [ %dec.6.4, %loop.6.4 ], [ %iv.next121, %loop.5.4 ] 459 %dec.6.4 = add i32 %d.4.6.4, -1 460 br label %loop.6.4 461} 462