xref: /llvm-project/llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-postinc-pos-addrspace.ll (revision 9e9907f1cfa424366fba58d9520f9305b537cec9) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -mtriple=amdgcn -mcpu=bonaire -loop-reduce -S < %s | FileCheck %s
3
4; Test various conditions where OptimizeLoopTermCond doesn't look at a
5; memory instruction use and fails to find the address space.
6
7target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
8
9define amdgpu_kernel void @local_cmp_user(i32 %arg0) nounwind {
10; CHECK-LABEL: @local_cmp_user(
11; CHECK-NEXT:  entry:
12; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[ARG0:%.*]], 1
13; CHECK-NEXT:    br label [[BB11:%.*]]
14; CHECK:       bb11:
15; CHECK-NEXT:    [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[BB:%.*]] ], [ -2, [[ENTRY:%.*]] ]
16; CHECK-NEXT:    [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[BB]] ], [ [[TMP0]], [[ENTRY]] ]
17; CHECK-NEXT:    [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], -1
18; CHECK-NEXT:    [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], 2
19; CHECK-NEXT:    [[C0:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], 0
20; CHECK-NEXT:    br i1 [[C0]], label [[BB13:%.*]], label [[BB]]
21; CHECK:       bb:
22; CHECK-NEXT:    [[T:%.*]] = load ptr addrspace(3), ptr addrspace(3) undef, align 4
23; CHECK-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(3) [[T]], i32 [[LSR_IV_NEXT2]]
24; CHECK-NEXT:    [[C1:%.*]] = icmp ne ptr addrspace(3) [[SCEVGEP]], null
25; CHECK-NEXT:    br i1 [[C1]], label [[BB11]], label [[BB13]]
26; CHECK:       bb13:
27; CHECK-NEXT:    unreachable
28;
29entry:
30  br label %bb11
31
32bb11:                                             ; preds = %bb, %entry
33  %i = phi i32 [ 0, %entry ], [ %i.next, %bb ]
34  %ii = shl i32 %i, 1
35  %c0 = icmp eq i32 %i, %arg0
36  br i1 %c0, label %bb13, label %bb
37
38bb:                                               ; preds = %bb11
39  %t = load ptr addrspace(3), ptr addrspace(3) undef, align 4
40  %p = getelementptr i8, ptr addrspace(3) %t, i32 %ii
41  %c1 = icmp ne ptr addrspace(3) %p, null
42  %i.next = add i32 %i, 1
43  br i1 %c1, label %bb11, label %bb13
44
45bb13:                                             ; preds = %bb, %bb11
46  unreachable
47}
48
49define amdgpu_kernel void @global_cmp_user(i64 %arg0) nounwind {
50; CHECK-LABEL: @global_cmp_user(
51; CHECK-NEXT:  entry:
52; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[ARG0:%.*]], 1
53; CHECK-NEXT:    br label [[BB11:%.*]]
54; CHECK:       bb11:
55; CHECK-NEXT:    [[LSR_IV1:%.*]] = phi i64 [ [[LSR_IV_NEXT2:%.*]], [[BB:%.*]] ], [ -2, [[ENTRY:%.*]] ]
56; CHECK-NEXT:    [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[BB]] ], [ [[TMP0]], [[ENTRY]] ]
57; CHECK-NEXT:    [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -1
58; CHECK-NEXT:    [[LSR_IV_NEXT2]] = add i64 [[LSR_IV1]], 2
59; CHECK-NEXT:    [[C0:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0
60; CHECK-NEXT:    br i1 [[C0]], label [[BB13:%.*]], label [[BB]]
61; CHECK:       bb:
62; CHECK-NEXT:    [[T:%.*]] = load ptr addrspace(1), ptr addrspace(1) undef, align 8
63; CHECK-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(1) [[T]], i64 [[LSR_IV_NEXT2]]
64; CHECK-NEXT:    [[C1:%.*]] = icmp ne ptr addrspace(1) [[SCEVGEP]], null
65; CHECK-NEXT:    br i1 [[C1]], label [[BB11]], label [[BB13]]
66; CHECK:       bb13:
67; CHECK-NEXT:    unreachable
68;
69entry:
70  br label %bb11
71
72bb11:                                             ; preds = %bb, %entry
73  %i = phi i64 [ 0, %entry ], [ %i.next, %bb ]
74  %ii = shl i64 %i, 1
75  %c0 = icmp eq i64 %i, %arg0
76  br i1 %c0, label %bb13, label %bb
77
78bb:                                               ; preds = %bb11
79  %t = load ptr addrspace(1), ptr addrspace(1) undef, align 8
80  %p = getelementptr i8, ptr addrspace(1) %t, i64 %ii
81  %c1 = icmp ne ptr addrspace(1) %p, null
82  %i.next = add i64 %i, 1
83  br i1 %c1, label %bb11, label %bb13
84
85bb13:                                             ; preds = %bb, %bb11
86  unreachable
87}
88
89define amdgpu_kernel void @global_gep_user(i32 %arg0) nounwind {
90; CHECK-LABEL: @global_gep_user(
91; CHECK-NEXT:  entry:
92; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[ARG0:%.*]], 1
93; CHECK-NEXT:    br label [[BB11:%.*]]
94; CHECK:       bb11:
95; CHECK-NEXT:    [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[BB:%.*]] ], [ 0, [[ENTRY:%.*]] ]
96; CHECK-NEXT:    [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[BB]] ], [ [[TMP0]], [[ENTRY]] ]
97; CHECK-NEXT:    [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], -1
98; CHECK-NEXT:    [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], 2
99; CHECK-NEXT:    [[C0:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], 0
100; CHECK-NEXT:    br i1 [[C0]], label [[BB13:%.*]], label [[BB]]
101; CHECK:       bb:
102; CHECK-NEXT:    [[T:%.*]] = load ptr addrspace(1), ptr addrspace(1) undef, align 8
103; CHECK-NEXT:    [[IDXPROM:%.*]] = sext i32 [[LSR_IV1]] to i64
104; CHECK-NEXT:    [[P:%.*]] = getelementptr i8, ptr addrspace(1) [[T]], i64 [[IDXPROM]]
105; CHECK-NEXT:    [[C1:%.*]] = icmp ne ptr addrspace(1) [[P]], null
106; CHECK-NEXT:    br i1 [[C1]], label [[BB11]], label [[BB13]]
107; CHECK:       bb13:
108; CHECK-NEXT:    unreachable
109;
110entry:
111  br label %bb11
112
113bb11:                                             ; preds = %bb, %entry
114  %i = phi i32 [ 0, %entry ], [ %i.next, %bb ]
115  %ii = shl i32 %i, 1
116  %c0 = icmp eq i32 %i, %arg0
117  br i1 %c0, label %bb13, label %bb
118
119bb:                                               ; preds = %bb11
120  %t = load ptr addrspace(1), ptr addrspace(1) undef, align 8
121  %idxprom = sext i32 %ii to i64
122  %p = getelementptr i8, ptr addrspace(1) %t, i64 %idxprom
123  %c1 = icmp ne ptr addrspace(1) %p, null
124  %i.next = add i32 %i, 1
125  br i1 %c1, label %bb11, label %bb13
126
127bb13:                                             ; preds = %bb, %bb11
128  unreachable
129}
130
131define amdgpu_kernel void @global_sext_scale_user(i32 %arg0) nounwind {
132; CHECK-LABEL: @global_sext_scale_user(
133; CHECK-NEXT:  entry:
134; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[ARG0:%.*]], 1
135; CHECK-NEXT:    br label [[BB11:%.*]]
136; CHECK:       bb11:
137; CHECK-NEXT:    [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[BB:%.*]] ], [ 0, [[ENTRY:%.*]] ]
138; CHECK-NEXT:    [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[BB]] ], [ [[TMP0]], [[ENTRY]] ]
139; CHECK-NEXT:    [[II_EXT:%.*]] = sext i32 [[LSR_IV1]] to i64
140; CHECK-NEXT:    [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], -1
141; CHECK-NEXT:    [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], 2
142; CHECK-NEXT:    [[C0:%.*]] = icmp eq i32 [[LSR_IV_NEXT]], 0
143; CHECK-NEXT:    br i1 [[C0]], label [[BB13:%.*]], label [[BB]]
144; CHECK:       bb:
145; CHECK-NEXT:    [[T:%.*]] = load ptr addrspace(1), ptr addrspace(1) undef, align 8
146; CHECK-NEXT:    [[P:%.*]] = getelementptr i8, ptr addrspace(1) [[T]], i64 [[II_EXT]]
147; CHECK-NEXT:    [[C1:%.*]] = icmp ne ptr addrspace(1) [[P]], null
148; CHECK-NEXT:    br i1 [[C1]], label [[BB11]], label [[BB13]]
149; CHECK:       bb13:
150; CHECK-NEXT:    unreachable
151;
152entry:
153  br label %bb11
154
155bb11:                                             ; preds = %bb, %entry
156  %i = phi i32 [ 0, %entry ], [ %i.next, %bb ]
157  %ii = shl i32 %i, 1
158  %ii.ext = sext i32 %ii to i64
159  %c0 = icmp eq i32 %i, %arg0
160  br i1 %c0, label %bb13, label %bb
161
162bb:                                               ; preds = %bb11
163  %t = load ptr addrspace(1), ptr addrspace(1) undef, align 8
164  %p = getelementptr i8, ptr addrspace(1) %t, i64 %ii.ext
165  %c1 = icmp ne ptr addrspace(1) %p, null
166  %i.next = add i32 %i, 1
167  br i1 %c1, label %bb11, label %bb13
168
169bb13:                                             ; preds = %bb, %bb11
170  unreachable
171}
172