xref: /llvm-project/llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll (revision ddb46abd3c8b33d7213dd96ec70e1f92336f467e)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=arm64-unknown-unknown -mcpu=cyclone -pre-RA-sched=list-hybrid < %s | FileCheck %s
3; rdar://10232252
4; Prevent LSR of doing poor choice that cannot be folded in addressing mode
5
6; Remove the -pre-RA-sched=list-hybrid option after fixing:
7; <rdar://problem/12702735> [ARM64][coalescer] need better register
8; coalescing for simple unit tests.
9
10define i32 @test_inttoptr() nounwind {
11; CHECK-LABEL: test_inttoptr:
12; CHECK:       // %bb.0: // %entry
13; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
14; CHECK-NEXT:    mov w8, #1288 // =0x508
15; CHECK-NEXT:    mov x9, #4294967296 // =0x100000000
16; CHECK-NEXT:    mov x10, #6442450944 // =0x180000000
17; CHECK-NEXT:  .LBB0_1: // %while.body
18; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
19; CHECK-NEXT:    ldr x11, [x9], #8
20; CHECK-NEXT:    str x11, [x10], #8
21; CHECK-NEXT:    subs x8, x8, #8
22; CHECK-NEXT:    b.pl .LBB0_1
23; CHECK-NEXT:  // %bb.2: // %while.end
24; CHECK-NEXT:    mov x8, #6442450944 // =0x180000000
25; CHECK-NEXT:    blr x8
26; CHECK-NEXT:    mov w0, #0 // =0x0
27; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
28; CHECK-NEXT:    ret
29entry:
30  br label %while.body
31
32while.body:                                       ; preds = %while.body, %entry
33  %len.06 = phi i64 [ 1288, %entry ], [ %sub, %while.body ]
34  %pDst.05 = phi ptr [ inttoptr (i64 6442450944 to ptr), %entry ], [ %incdec.ptr1, %while.body ]
35  %pSrc.04 = phi ptr [ inttoptr (i64 4294967296 to ptr), %entry ], [ %incdec.ptr, %while.body ]
36  %incdec.ptr = getelementptr inbounds i64, ptr %pSrc.04, i64 1
37  %tmp = load volatile i64, ptr %pSrc.04, align 8
38  %incdec.ptr1 = getelementptr inbounds i64, ptr %pDst.05, i64 1
39  store volatile i64 %tmp, ptr %pDst.05, align 8
40  %sub = add i64 %len.06, -8
41  %cmp = icmp sgt i64 %sub, -1
42  br i1 %cmp, label %while.body, label %while.end
43
44while.end:                                        ; preds = %while.body
45  tail call void inttoptr (i64 6442450944 to ptr)() nounwind
46  ret i32 0
47}
48
49@g1 = external dso_local global i8
50@g2 = external dso_local global i8
51
52define ptr @test_globals() nounwind {
53; CHECK-LABEL: test_globals:
54; CHECK:       // %bb.0: // %entry
55; CHECK-NEXT:    mov w8, #1288 // =0x508
56; CHECK-NEXT:    adrp x9, g2
57; CHECK-NEXT:    add x9, x9, :lo12:g2
58; CHECK-NEXT:    adrp x10, g1
59; CHECK-NEXT:    add x10, x10, :lo12:g1
60; CHECK-NEXT:  .LBB1_1: // %while.body
61; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
62; CHECK-NEXT:    ldr x11, [x9], #8
63; CHECK-NEXT:    str x11, [x10], #8
64; CHECK-NEXT:    subs x8, x8, #8
65; CHECK-NEXT:    b.pl .LBB1_1
66; CHECK-NEXT:  // %bb.2: // %while.end
67; CHECK-NEXT:    adrp x0, g1
68; CHECK-NEXT:    add x0, x0, :lo12:g1
69; CHECK-NEXT:    ret
70entry:
71  br label %while.body
72
73while.body:                                       ; preds = %while.body, %entry
74  %len.06 = phi i64 [ 1288, %entry ], [ %sub, %while.body ]
75  %pDst.05 = phi ptr [ @g1, %entry ], [ %incdec.ptr1, %while.body ]
76  %pSrc.04 = phi ptr [ @g2, %entry ], [ %incdec.ptr, %while.body ]
77  %incdec.ptr = getelementptr inbounds i64, ptr %pSrc.04, i64 1
78  %tmp = load volatile i64, ptr %pSrc.04, align 8
79  %incdec.ptr1 = getelementptr inbounds i64, ptr %pDst.05, i64 1
80  store volatile i64 %tmp, ptr %pDst.05, align 8
81  %sub = add i64 %len.06, -8
82  %cmp = icmp sgt i64 %sub, -1
83  br i1 %cmp, label %while.body, label %while.end
84
85while.end:                                        ; preds = %while.body
86  ret ptr @g1
87}
88