1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -S -passes=loop-rotate -o - -verify-loop-info -verify-dom-info | FileCheck %s 3 4@d = external global i64, align 8 5@f = external global i32, align 4 6@g = external global i32, align 4 7@i = external global i32, align 4 8@h = external global i32, align 4 9 10define i32 @o() #0 { 11; CHECK-LABEL: @o( 12; CHECK-NEXT: bb: 13; CHECK-NEXT: [[I:%.*]] = alloca [1 x i32], align 4 14; CHECK-NEXT: [[I1:%.*]] = load ptr, ptr @d, align 8 15; CHECK-NEXT: [[I33:%.*]] = load i32, ptr @f, align 4 16; CHECK-NEXT: [[I44:%.*]] = icmp eq i32 [[I33]], 0 17; CHECK-NEXT: br i1 [[I44]], label [[BB15:%.*]], label [[BB5_LR_PH:%.*]] 18; CHECK: bb5.lr.ph: 19; CHECK-NEXT: br label [[BB5:%.*]] 20; CHECK: bb5: 21; CHECK-NEXT: [[I35:%.*]] = phi i32 [ [[I33]], [[BB5_LR_PH]] ], [ [[I3:%.*]], [[M_EXIT:%.*]] ] 22; CHECK-NEXT: [[I6:%.*]] = icmp ult i32 [[I35]], 4 23; CHECK-NEXT: [[I7:%.*]] = zext i1 [[I6]] to i32 24; CHECK-NEXT: store i32 [[I7]], ptr @g, align 4 25; CHECK-NEXT: [[I9:%.*]] = call i32 @n(ptr nonnull [[I]], ptr [[I1]]) 26; CHECK-NEXT: [[I10:%.*]] = icmp eq i32 [[I9]], 0 27; CHECK-NEXT: br i1 [[I10]], label [[THREAD_PRE_SPLIT:%.*]], label [[BB5_BB15_CRIT_EDGE:%.*]] 28; CHECK: thread-pre-split: 29; CHECK-NEXT: [[DOTPR:%.*]] = load i32, ptr @i, align 4 30; CHECK-NEXT: [[I12:%.*]] = icmp eq i32 [[DOTPR]], 0 31; CHECK-NEXT: br i1 [[I12]], label [[M_EXIT]], label [[BB13_LR_PH:%.*]] 32; CHECK: bb13.lr.ph: 33; CHECK-NEXT: br label [[BB13:%.*]] 34; CHECK: bb13: 35; CHECK-NEXT: [[DOT11:%.*]] = phi i32 [ undef, [[BB13_LR_PH]] ], [ [[I14:%.*]], [[J_EXIT_I:%.*]] ] 36; CHECK-NEXT: callbr void asm sideeffect "", "!i,~{dirflag},~{fpsr},~{flags}"() #[[ATTR1:[0-9]+]] 37; CHECK-NEXT: to label [[J_EXIT_I]] [label %bb13.m.exit_crit_edge] 38; CHECK: j.exit.i: 39; CHECK-NEXT: [[I14]] = tail call i32 asm "", "={ax},~{dirflag},~{fpsr},~{flags}"() #[[ATTR2:[0-9]+]] 40; CHECK-NEXT: br i1 [[I12]], label [[BB11_M_EXIT_CRIT_EDGE:%.*]], label [[BB13]] 41; CHECK: bb13.m.exit_crit_edge: 42; CHECK-NEXT: [[SPLIT:%.*]] = phi i32 [ [[DOT11]], [[BB13]] ] 43; CHECK-NEXT: br label [[M_EXIT]] 44; CHECK: bb11.m.exit_crit_edge: 45; CHECK-NEXT: [[SPLIT2:%.*]] = phi i32 [ [[I14]], [[J_EXIT_I]] ] 46; CHECK-NEXT: br label [[M_EXIT]] 47; CHECK: m.exit: 48; CHECK-NEXT: [[DOT1_LCSSA:%.*]] = phi i32 [ [[SPLIT]], [[BB13_M_EXIT_CRIT_EDGE:%.*]] ], [ [[SPLIT2]], [[BB11_M_EXIT_CRIT_EDGE]] ], [ undef, [[THREAD_PRE_SPLIT]] ] 49; CHECK-NEXT: store i32 [[DOT1_LCSSA]], ptr @h, align 4 50; CHECK-NEXT: [[I3]] = load i32, ptr @f, align 4 51; CHECK-NEXT: [[I4:%.*]] = icmp eq i32 [[I3]], 0 52; CHECK-NEXT: br i1 [[I4]], label [[BB2_BB15_CRIT_EDGE:%.*]], label [[BB5]] 53; CHECK: bb5.bb15_crit_edge: 54; CHECK-NEXT: br label [[BB15]] 55; CHECK: bb2.bb15_crit_edge: 56; CHECK-NEXT: br label [[BB15]] 57; CHECK: bb15: 58; CHECK-NEXT: ret i32 undef 59; 60bb: 61 %i = alloca [1 x i32], align 4 62 %i1 = load ptr, ptr @d, align 8 63 br label %bb2 64 65bb2: ; preds = %m.exit, %bb 66 %i3 = load i32, ptr @f, align 4 67 %i4 = icmp eq i32 %i3, 0 68 br i1 %i4, label %bb15, label %bb5 69 70bb5: ; preds = %bb2 71 %i6 = icmp ult i32 %i3, 4 72 %i7 = zext i1 %i6 to i32 73 store i32 %i7, ptr @g, align 4 74 %i9 = call i32 @n(ptr nonnull %i, ptr %i1) 75 %i10 = icmp eq i32 %i9, 0 76 br i1 %i10, label %thread-pre-split, label %bb15 77 78thread-pre-split: ; preds = %bb5 79 %.pr = load i32, ptr @i, align 4 80 br label %bb11 81 82bb11: ; preds = %j.exit.i, %thread-pre-split 83 %.1 = phi i32 [ %i14, %j.exit.i ], [ undef, %thread-pre-split ] 84 %i12 = icmp eq i32 %.pr, 0 85 br i1 %i12, label %m.exit, label %bb13 86 87bb13: ; preds = %bb11 88 callbr void asm sideeffect "", "!i,~{dirflag},~{fpsr},~{flags}"() #1 89 to label %j.exit.i [label %m.exit] 90 91j.exit.i: ; preds = %bb13 92 %i14 = tail call i32 asm "", "={ax},~{dirflag},~{fpsr},~{flags}"() #2 93 br label %bb11 94 95m.exit: ; preds = %bb13, %bb11 96 %.1.lcssa = phi i32 [ %.1, %bb13 ], [ %.1, %bb11 ] 97 store i32 %.1.lcssa, ptr @h, align 4 98 br label %bb2 99 100bb15: ; preds = %bb5, %bb2 101 ret i32 undef 102} 103 104declare i32 @n(ptr, ptr) #0 105 106attributes #0 = { "use-soft-float"="false" } 107attributes #1 = { nounwind } 108attributes #2 = { nounwind readnone } 109