xref: /llvm-project/llvm/test/Transforms/InstSimplify/ConstProp/active-lane-mask.ll (revision 38fffa630ee80163dc65e759392ad29798905679) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -passes=instsimplify -S -o - %s | FileCheck %s
3
4target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
5
6define <16 x i1> @v16i1_0() {
7; CHECK-LABEL: @v16i1_0(
8; CHECK-NEXT:  entry:
9; CHECK-NEXT:    ret <16 x i1> zeroinitializer
10;
11entry:
12  %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 0)
13  ret <16 x i1> %int
14}
15
16define <16 x i1> @v16i1_1() {
17; CHECK-LABEL: @v16i1_1(
18; CHECK-NEXT:  entry:
19; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
20;
21entry:
22  %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 1)
23  ret <16 x i1> %int
24}
25
26define <16 x i1> @v16i1_8() {
27; CHECK-LABEL: @v16i1_8(
28; CHECK-NEXT:  entry:
29; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
30;
31entry:
32  %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 8)
33  ret <16 x i1> %int
34}
35
36define <16 x i1> @v16i1_15() {
37; CHECK-LABEL: @v16i1_15(
38; CHECK-NEXT:  entry:
39; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false>
40;
41entry:
42  %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 15)
43  ret <16 x i1> %int
44}
45
46define <16 x i1> @v16i1_16() {
47; CHECK-LABEL: @v16i1_16(
48; CHECK-NEXT:  entry:
49; CHECK-NEXT:    ret <16 x i1> splat (i1 true)
50;
51entry:
52  %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 16)
53  ret <16 x i1> %int
54}
55
56define <16 x i1> @v16i1_100() {
57; CHECK-LABEL: @v16i1_100(
58; CHECK-NEXT:  entry:
59; CHECK-NEXT:    ret <16 x i1> splat (i1 true)
60;
61entry:
62  %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 100)
63  ret <16 x i1> %int
64}
65
66define <16 x i1> @v16i1_m1() {
67; CHECK-LABEL: @v16i1_m1(
68; CHECK-NEXT:  entry:
69; CHECK-NEXT:    ret <16 x i1> splat (i1 true)
70;
71entry:
72  %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 -1)
73  ret <16 x i1> %int
74}
75
76define <16 x i1> @v16i1_10_11() {
77; CHECK-LABEL: @v16i1_10_11(
78; CHECK-NEXT:  entry:
79; CHECK-NEXT:    ret <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
80;
81entry:
82  %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 10, i32 11)
83  ret <16 x i1> %int
84}
85
86define <16 x i1> @v16i1_12_11() {
87; CHECK-LABEL: @v16i1_12_11(
88; CHECK-NEXT:  entry:
89; CHECK-NEXT:    ret <16 x i1> zeroinitializer
90;
91entry:
92  %int = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 12, i32 11)
93  ret <16 x i1> %int
94}
95
96
97
98define <8 x i1> @v8i1_0() {
99; CHECK-LABEL: @v8i1_0(
100; CHECK-NEXT:  entry:
101; CHECK-NEXT:    ret <8 x i1> zeroinitializer
102;
103entry:
104  %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 0)
105  ret <8 x i1> %int
106}
107
108define <8 x i1> @v8i1_1() {
109; CHECK-LABEL: @v8i1_1(
110; CHECK-NEXT:  entry:
111; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
112;
113entry:
114  %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 1)
115  ret <8 x i1> %int
116}
117
118define <8 x i1> @v8i1_4() {
119; CHECK-LABEL: @v8i1_4(
120; CHECK-NEXT:  entry:
121; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
122;
123entry:
124  %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 4)
125  ret <8 x i1> %int
126}
127
128define <8 x i1> @v8i1_7() {
129; CHECK-LABEL: @v8i1_7(
130; CHECK-NEXT:  entry:
131; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false>
132;
133entry:
134  %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 7)
135  ret <8 x i1> %int
136}
137
138define <8 x i1> @v8i1_8() {
139; CHECK-LABEL: @v8i1_8(
140; CHECK-NEXT:  entry:
141; CHECK-NEXT:    ret <8 x i1> splat (i1 true)
142;
143entry:
144  %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 8)
145  ret <8 x i1> %int
146}
147
148define <8 x i1> @v8i1_100() {
149; CHECK-LABEL: @v8i1_100(
150; CHECK-NEXT:  entry:
151; CHECK-NEXT:    ret <8 x i1> splat (i1 true)
152;
153entry:
154  %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 100)
155  ret <8 x i1> %int
156}
157
158define <8 x i1> @v8i1_m1() {
159; CHECK-LABEL: @v8i1_m1(
160; CHECK-NEXT:  entry:
161; CHECK-NEXT:    ret <8 x i1> splat (i1 true)
162;
163entry:
164  %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 0, i32 -1)
165  ret <8 x i1> %int
166}
167
168define <8 x i1> @v8i1_10_11() {
169; CHECK-LABEL: @v8i1_10_11(
170; CHECK-NEXT:  entry:
171; CHECK-NEXT:    ret <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>
172;
173entry:
174  %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 10, i32 11)
175  ret <8 x i1> %int
176}
177
178define <8 x i1> @v8i1_12_11() {
179; CHECK-LABEL: @v8i1_12_11(
180; CHECK-NEXT:  entry:
181; CHECK-NEXT:    ret <8 x i1> zeroinitializer
182;
183entry:
184  %int = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 12, i32 11)
185  ret <8 x i1> %int
186}
187
188
189
190define <4 x i1> @v4i1_0() {
191; CHECK-LABEL: @v4i1_0(
192; CHECK-NEXT:  entry:
193; CHECK-NEXT:    ret <4 x i1> zeroinitializer
194;
195entry:
196  %int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 0)
197  ret <4 x i1> %int
198}
199
200define <4 x i1> @v4i1_1() {
201; CHECK-LABEL: @v4i1_1(
202; CHECK-NEXT:  entry:
203; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 false, i1 false, i1 false>
204;
205entry:
206  %int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 1)
207  ret <4 x i1> %int
208}
209
210define <4 x i1> @v4i1_3() {
211; CHECK-LABEL: @v4i1_3(
212; CHECK-NEXT:  entry:
213; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 false>
214;
215entry:
216  %int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 3)
217  ret <4 x i1> %int
218}
219
220define <4 x i1> @v4i1_4() {
221; CHECK-LABEL: @v4i1_4(
222; CHECK-NEXT:  entry:
223; CHECK-NEXT:    ret <4 x i1> splat (i1 true)
224;
225entry:
226  %int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 4)
227  ret <4 x i1> %int
228}
229
230define <4 x i1> @v4i1_100() {
231; CHECK-LABEL: @v4i1_100(
232; CHECK-NEXT:  entry:
233; CHECK-NEXT:    ret <4 x i1> splat (i1 true)
234;
235entry:
236  %int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 100)
237  ret <4 x i1> %int
238}
239
240define <4 x i1> @v4i1_m1() {
241; CHECK-LABEL: @v4i1_m1(
242; CHECK-NEXT:  entry:
243; CHECK-NEXT:    ret <4 x i1> splat (i1 true)
244;
245entry:
246  %int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 0, i32 -1)
247  ret <4 x i1> %int
248}
249
250define <4 x i1> @v4i1_10_11() {
251; CHECK-LABEL: @v4i1_10_11(
252; CHECK-NEXT:  entry:
253; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 false, i1 false, i1 false>
254;
255entry:
256  %int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 10, i32 11)
257  ret <4 x i1> %int
258}
259
260define <4 x i1> @v4i1_12_11() {
261; CHECK-LABEL: @v4i1_12_11(
262; CHECK-NEXT:  entry:
263; CHECK-NEXT:    ret <4 x i1> zeroinitializer
264;
265entry:
266  %int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 12, i32 11)
267  ret <4 x i1> %int
268}
269
270
271
272define <4 x i1> @v4i1_nc1(i32 %x) {
273; CHECK-LABEL: @v4i1_nc1(
274; CHECK-NEXT:  entry:
275; CHECK-NEXT:    [[INT:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[X:%.*]], i32 11)
276; CHECK-NEXT:    ret <4 x i1> [[INT]]
277;
278entry:
279  %int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %x, i32 11)
280  ret <4 x i1> %int
281}
282
283define <4 x i1> @v4i1_nc2(i32 %x) {
284; CHECK-LABEL: @v4i1_nc2(
285; CHECK-NEXT:  entry:
286; CHECK-NEXT:    [[INT:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 11, i32 [[X:%.*]])
287; CHECK-NEXT:    ret <4 x i1> [[INT]]
288;
289entry:
290  %int = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 11, i32 %x)
291  ret <4 x i1> %int
292}
293
294
295define <4 x float> @poisonc(<4 x float> %a, i32 %n) {
296; CHECK-LABEL: @poisonc(
297; CHECK-NEXT:  entry:
298; CHECK-NEXT:    [[VAR27:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 poison, i32 1024)
299; CHECK-NEXT:    [[VAR33:%.*]] = select <4 x i1> [[VAR27]], <4 x float> [[A:%.*]], <4 x float> zeroinitializer
300; CHECK-NEXT:    ret <4 x float> [[VAR33]]
301;
302entry:
303  %new0 = shl i1 0, 1
304  %last = zext i1 %new0 to i32
305  %var27 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %last, i32 1024)
306  %var33 = select <4 x i1> %var27, <4 x float> %a, <4 x float> zeroinitializer
307  ret <4 x float> %var33
308}
309
310declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
311declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
312declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
313