1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes=instcombine -S | FileCheck %s 3 4define i8 @zext_or_icmp_icmp(i8 %a, i8 %b) { 5; CHECK-LABEL: @zext_or_icmp_icmp( 6; CHECK-NEXT: [[MASK:%.*]] = and i8 [[A:%.*]], 1 7; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp eq i8 [[MASK]], 0 8; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp eq i8 [[B:%.*]], 0 9; CHECK-NEXT: [[BOTHCOND:%.*]] = or i1 [[TOBOOL1]], [[TOBOOL2]] 10; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[BOTHCOND]] to i8 11; CHECK-NEXT: ret i8 [[ZEXT]] 12; 13 %mask = and i8 %a, 1 14 %toBool1 = icmp eq i8 %mask, 0 15 %toBool2 = icmp eq i8 %b, 0 16 %bothCond = or i1 %toBool1, %toBool2 17 %zext = zext i1 %bothCond to i8 18 ret i8 %zext 19} 20 21define i8 @zext_or_icmp_icmp_logical(i8 %a, i8 %b) { 22; CHECK-LABEL: @zext_or_icmp_icmp_logical( 23; CHECK-NEXT: [[MASK:%.*]] = and i8 [[A:%.*]], 1 24; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp eq i8 [[MASK]], 0 25; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp eq i8 [[B:%.*]], 0 26; CHECK-NEXT: [[BOTHCOND:%.*]] = select i1 [[TOBOOL1]], i1 true, i1 [[TOBOOL2]] 27; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[BOTHCOND]] to i8 28; CHECK-NEXT: ret i8 [[ZEXT]] 29; 30 %mask = and i8 %a, 1 31 %toBool1 = icmp eq i8 %mask, 0 32 %toBool2 = icmp eq i8 %b, 0 33 %bothCond = select i1 %toBool1, i1 true, i1 %toBool2 34 %zext = zext i1 %bothCond to i8 35 ret i8 %zext 36} 37 38; Here, widening the or from i1 to i32 and removing one of the icmps would 39; widen an undef value (created by the out-of-range shift), increasing the 40; range of valid values for the return, so we can't do it. 41 42define i32 @dont_widen_undef() { 43; CHECK-LABEL: @dont_widen_undef( 44; CHECK-NEXT: entry: 45; CHECK-NEXT: br label [[BLOCK2:%.*]] 46; CHECK: block1: 47; CHECK-NEXT: br label [[BLOCK2]] 48; CHECK: block2: 49; CHECK-NEXT: ret i32 1 50; 51entry: 52 br label %block2 53 54block1: 55 br label %block2 56 57block2: 58 %m.011 = phi i32 [ 33, %entry ], [ 0, %block1 ] 59 %cmp.i = icmp ugt i32 %m.011, 1 60 %m.1.op = lshr i32 1, %m.011 61 %sext.mask = and i32 %m.1.op, 65535 62 %cmp115 = icmp ne i32 %sext.mask, 0 63 %cmp1 = or i1 %cmp.i, %cmp115 64 %conv2 = zext i1 %cmp1 to i32 65 ret i32 %conv2 66} 67 68define i32 @dont_widen_undef_logical() { 69; CHECK-LABEL: @dont_widen_undef_logical( 70; CHECK-NEXT: entry: 71; CHECK-NEXT: br label [[BLOCK2:%.*]] 72; CHECK: block1: 73; CHECK-NEXT: br label [[BLOCK2]] 74; CHECK: block2: 75; CHECK-NEXT: ret i32 1 76; 77entry: 78 br label %block2 79 80block1: 81 br label %block2 82 83block2: 84 %m.011 = phi i32 [ 33, %entry ], [ 0, %block1 ] 85 %cmp.i = icmp ugt i32 %m.011, 1 86 %m.1.op = lshr i32 1, %m.011 87 %sext.mask = and i32 %m.1.op, 65535 88 %cmp115 = icmp ne i32 %sext.mask, 0 89 %cmp1 = select i1 %cmp.i, i1 true, i1 %cmp115 90 %conv2 = zext i1 %cmp1 to i32 91 ret i32 %conv2 92} 93 94; A limitation of knownbits with overshift prevents reducing to 'false'. 95 96define i1 @knownbits_out_of_range_shift(i32 %x) { 97; CHECK-LABEL: @knownbits_out_of_range_shift( 98; CHECK-NEXT: entry: 99; CHECK-NEXT: br label [[BLOCK2:%.*]] 100; CHECK: block1: 101; CHECK-NEXT: br label [[BLOCK2]] 102; CHECK: block2: 103; CHECK-NEXT: ret i1 false 104; 105entry: 106 br label %block2 107 108block1: 109 br label %block2 110 111block2: 112 %p = phi i32 [ 63, %entry ], [ 31, %block1 ] 113 %l = lshr i32 %x, %p 114 %r = icmp eq i32 %l, 2 115 ret i1 %r 116} 117 118; PR43261 119 120define i32 @zext_or_eq_ult_add(i32 %i) { 121; CHECK-LABEL: @zext_or_eq_ult_add( 122; CHECK-NEXT: [[A:%.*]] = add i32 [[I:%.*]], -3 123; CHECK-NEXT: [[C1:%.*]] = icmp ult i32 [[A]], 3 124; CHECK-NEXT: [[R:%.*]] = zext i1 [[C1]] to i32 125; CHECK-NEXT: ret i32 [[R]] 126; 127 %a = add i32 %i, -3 128 %c1 = icmp ult i32 %a, 3 129 %c2 = icmp eq i32 %i, 5 130 %o = or i1 %c1, %c2 131 %r = zext i1 %o to i32 132 ret i32 %r 133} 134 135define i32 @select_zext_or_eq_ult_add(i32 %i) { 136; CHECK-LABEL: @select_zext_or_eq_ult_add( 137; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[I:%.*]], -3 138; CHECK-NEXT: [[NARROW:%.*]] = icmp ult i32 [[TMP1]], 3 139; CHECK-NEXT: [[R:%.*]] = zext i1 [[NARROW]] to i32 140; CHECK-NEXT: ret i32 [[R]] 141; 142 %a = add i32 %i, -3 143 %c1 = icmp ult i32 %a, 2 144 %c2 = icmp eq i32 %i, 5 145 %z = zext i1 %c2 to i32 146 %r = select i1 %c1, i32 1, i32 %z 147 ret i32 %r 148} 149 150; This should not end with more instructions than it started from. 151 152define i32 @PR49475(i32 %x, i16 %y) { 153; CHECK-LABEL: @PR49475( 154; CHECK-NEXT: [[M:%.*]] = and i16 [[Y:%.*]], 1 155; CHECK-NEXT: [[B1:%.*]] = icmp eq i32 [[X:%.*]], 0 156; CHECK-NEXT: [[B2:%.*]] = icmp eq i16 [[M]], 0 157; CHECK-NEXT: [[T1:%.*]] = or i1 [[B1]], [[B2]] 158; CHECK-NEXT: [[Z:%.*]] = zext i1 [[T1]] to i32 159; CHECK-NEXT: ret i32 [[Z]] 160; 161 %m = and i16 %y, 1 162 %b1 = icmp eq i32 %x, 0 163 %b2 = icmp eq i16 %m, 0 164 %t1 = or i1 %b1, %b2 165 %z = zext i1 %t1 to i32 166 ret i32 %z 167} 168 169; This would infinite-loop. 170 171define i8 @PR49475_infloop(i32 %t0, i16 %insert, i64 %e, i8 %i162) "instcombine-no-verify-fixpoint" { 172; CHECK-LABEL: @PR49475_infloop( 173; CHECK-NEXT: [[B2:%.*]] = icmp eq i16 [[INSERT:%.*]], 0 174; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[T0:%.*]], 1 175; CHECK-NEXT: [[TMP2:%.*]] = or disjoint i32 [[TMP1]], 140 176; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 177; CHECK-NEXT: [[XOR:%.*]] = select i1 [[B2]], i64 [[TMP3]], i64 140 178; CHECK-NEXT: [[CONV16:%.*]] = sext i8 [[I162:%.*]] to i64 179; CHECK-NEXT: [[SUB17:%.*]] = sub i64 [[CONV16]], [[E:%.*]] 180; CHECK-NEXT: [[SEXT:%.*]] = shl i64 [[SUB17]], 32 181; CHECK-NEXT: [[CONV18:%.*]] = ashr exact i64 [[SEXT]], 32 182; CHECK-NEXT: [[CMP:%.*]] = icmp sge i64 [[XOR]], [[CONV18]] 183; CHECK-NEXT: [[TRUNC44:%.*]] = zext i1 [[CMP]] to i8 184; CHECK-NEXT: [[INC:%.*]] = add i8 [[I162]], [[TRUNC44]] 185; CHECK-NEXT: [[TOBOOL23_NOT:%.*]] = xor i1 [[CMP]], true 186; CHECK-NEXT: call void @llvm.assume(i1 [[TOBOOL23_NOT]]) 187; CHECK-NEXT: ret i8 [[INC]] 188; 189 %b = icmp eq i32 %t0, 0 190 %b2 = icmp eq i16 %insert, 0 191 %t1 = or i1 %b, %b2 192 %ext = zext i1 %t1 to i32 193 %and = and i32 %t0, %ext 194 %conv13 = zext i32 %and to i64 195 %xor = xor i64 %conv13, 140 196 %conv16 = sext i8 %i162 to i64 197 %sub17 = sub i64 %conv16, %e 198 %sext = shl i64 %sub17, 32 199 %conv18 = ashr exact i64 %sext, 32 200 %cmp = icmp sge i64 %xor, %conv18 201 %conv19 = zext i1 %cmp to i16 202 %or21 = or i16 %insert, %conv19 203 %trunc44 = trunc i16 %or21 to i8 204 %inc = add i8 %i162, %trunc44 205 %tobool23.not = icmp eq i16 %or21, 0 206 call void @llvm.assume(i1 %tobool23.not) 207 ret i8 %inc 208} 209 210; This would infinite loop because knownbits changed between checking 211; if a transform was profitable and actually doing the transform. 212 213define i1 @PR51762(ptr %i, i32 %t0, i16 %t1, ptr %p, ptr %d, ptr %f, i32 %p2, i1 %c1) { 214; CHECK-LABEL: @PR51762( 215; CHECK-NEXT: entry: 216; CHECK-NEXT: br label [[FOR_COND:%.*]] 217; CHECK: for.cond: 218; CHECK-NEXT: [[I_SROA_8_0:%.*]] = phi i32 [ poison, [[ENTRY:%.*]] ], [ [[I_SROA_8_0_EXTRACT_TRUNC:%.*]], [[COND_TRUE:%.*]] ] 219; CHECK-NEXT: br i1 [[C1:%.*]], label [[COND_TRUE]], label [[FOR_END11:%.*]] 220; CHECK: cond.true: 221; CHECK-NEXT: [[I_SROA_8_0_EXTRACT_TRUNC]] = ashr i32 [[T0:%.*]], 31 222; CHECK-NEXT: br label [[FOR_COND]] 223; CHECK: for.end11: 224; CHECK-NEXT: [[S1:%.*]] = sext i16 [[T1:%.*]] to i64 225; CHECK-NEXT: [[SROA38:%.*]] = load i32, ptr [[I:%.*]], align 8 226; CHECK-NEXT: [[INSERT_EXT51:%.*]] = zext i32 [[I_SROA_8_0]] to i64 227; CHECK-NEXT: [[INSERT_SHIFT52:%.*]] = shl nuw i64 [[INSERT_EXT51]], 32 228; CHECK-NEXT: [[INSERT_EXT39:%.*]] = zext i32 [[SROA38]] to i64 229; CHECK-NEXT: [[INSERT_INSERT41:%.*]] = or disjoint i64 [[INSERT_SHIFT52]], [[INSERT_EXT39]] 230; CHECK-NEXT: [[REM:%.*]] = urem i64 [[S1]], [[INSERT_INSERT41]] 231; CHECK-NEXT: [[NE:%.*]] = icmp ne i64 [[REM]], 0 232; CHECK-NEXT: [[LOR_EXT:%.*]] = zext i1 [[NE]] to i32 233; CHECK-NEXT: [[T2:%.*]] = load i32, ptr [[D:%.*]], align 4 234; CHECK-NEXT: [[CONV15:%.*]] = sext i16 [[T1]] to i32 235; CHECK-NEXT: [[CMP16:%.*]] = icmp sge i32 [[T2]], [[CONV15]] 236; CHECK-NEXT: [[CONV17:%.*]] = zext i1 [[CMP16]] to i32 237; CHECK-NEXT: [[T3:%.*]] = load i32, ptr [[F:%.*]], align 4 238; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[T3]], [[CONV17]] 239; CHECK-NEXT: store i32 [[ADD]], ptr [[F]], align 4 240; CHECK-NEXT: [[REM18:%.*]] = srem i32 [[LOR_EXT]], [[ADD]] 241; CHECK-NEXT: [[CONV19:%.*]] = zext nneg i32 [[REM18]] to i64 242; CHECK-NEXT: store i32 [[SROA38]], ptr [[D]], align 8 243; CHECK-NEXT: [[R:%.*]] = icmp ult i64 [[INSERT_INSERT41]], [[CONV19]] 244; CHECK-NEXT: call void @llvm.assume(i1 [[R]]) 245; CHECK-NEXT: ret i1 [[R]] 246; 247entry: 248 br label %for.cond 249 250for.cond: 251 %i.sroa.8.0 = phi i32 [ poison, %entry ], [ %i.sroa.8.0.extract.trunc, %cond.true ] 252 br i1 %c1, label %cond.true, label %for.end11 253 254cond.true: 255 %i.sroa.8.0.extract.trunc = ashr i32 %t0, 31 256 br label %for.cond 257 258for.end11: 259 %s1 = sext i16 %t1 to i64 260 %sroa38 = load i32, ptr %i, align 8 261 %insert.ext51 = zext i32 %i.sroa.8.0 to i64 262 %insert.shift52 = shl nuw i64 %insert.ext51, 32 263 %insert.ext39 = zext i32 %sroa38 to i64 264 %insert.insert41 = or i64 %insert.shift52, %insert.ext39 265 %rem = urem i64 %s1, %insert.insert41 266 %ne = icmp ne i64 %rem, 0 267 %cmp = icmp eq i64 %insert.insert41, 0 268 %spec.select57 = or i1 %ne, %cmp 269 270 %lor.ext = zext i1 %spec.select57 to i32 271 %t2 = load i32, ptr %d, align 4 272 %conv15 = sext i16 %t1 to i32 273 %cmp16 = icmp sge i32 %t2, %conv15 274 %conv17 = zext i1 %cmp16 to i32 275 %t3 = load i32, ptr %f, align 4 276 %add = add nsw i32 %t3, %conv17 277 store i32 %add, ptr %f, align 4 278 %rem18 = srem i32 %lor.ext, %add 279 %conv19 = zext i32 %rem18 to i64 280 %div = udiv i64 %insert.insert41, %conv19 281 %trunc33 = trunc i64 %div to i32 282 store i32 %trunc33, ptr %d, align 8 283 %r = icmp ult i64 %insert.insert41, %conv19 284 call void @llvm.assume(i1 %r) 285 ret i1 %r 286} 287 288declare void @llvm.assume(i1 noundef) 289