xref: /llvm-project/llvm/test/Transforms/InstCombine/switch-zext-sext.ll (revision 7c3bcc307a8fa9153a171f6abb4e8fdc91bd6030)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2; RUN: opt %s -passes=instcombine -S | FileCheck %s
3
4define i1 @test_switch_with_zext(i16 %a, i1 %b, i1 %c) {
5; CHECK-LABEL: define i1 @test_switch_with_zext(
6; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
7; CHECK-NEXT:  entry:
8; CHECK-NEXT:    switch i16 [[A]], label [[SW_DEFAULT:%.*]] [
9; CHECK-NEXT:      i16 37, label [[SW_BB:%.*]]
10; CHECK-NEXT:      i16 38, label [[SW_BB]]
11; CHECK-NEXT:      i16 39, label [[SW_BB]]
12; CHECK-NEXT:    ]
13; CHECK:       sw.bb:
14; CHECK-NEXT:    ret i1 [[B]]
15; CHECK:       sw.default:
16; CHECK-NEXT:    ret i1 [[C]]
17;
18entry:
19  %a.ext = zext i16 %a to i32
20  switch i32 %a.ext, label %sw.default [
21  i32 37, label %sw.bb
22  i32 38, label %sw.bb
23  i32 39, label %sw.bb
24  ]
25
26sw.bb:
27  ret i1 %b
28sw.default:
29  ret i1 %c
30}
31
32define i1 @test_switch_with_sext(i16 %a, i1 %b, i1 %c) {
33; CHECK-LABEL: define i1 @test_switch_with_sext(
34; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
35; CHECK-NEXT:  entry:
36; CHECK-NEXT:    switch i16 [[A]], label [[SW_DEFAULT:%.*]] [
37; CHECK-NEXT:      i16 37, label [[SW_BB:%.*]]
38; CHECK-NEXT:      i16 38, label [[SW_BB]]
39; CHECK-NEXT:      i16 39, label [[SW_BB]]
40; CHECK-NEXT:    ]
41; CHECK:       sw.bb:
42; CHECK-NEXT:    ret i1 [[B]]
43; CHECK:       sw.default:
44; CHECK-NEXT:    ret i1 [[C]]
45;
46entry:
47  %a.ext = sext i16 %a to i32
48  switch i32 %a.ext, label %sw.default [
49  i32 37, label %sw.bb
50  i32 38, label %sw.bb
51  i32 39, label %sw.bb
52  ]
53
54sw.bb:
55  ret i1 %b
56sw.default:
57  ret i1 %c
58}
59
60; Negative tests
61
62define i1 @test_switch_with_zext_unreachable_case(i16 %a, i1 %b, i1 %c) {
63; CHECK-LABEL: define i1 @test_switch_with_zext_unreachable_case(
64; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
65; CHECK-NEXT:  entry:
66; CHECK-NEXT:    [[A_EXT:%.*]] = zext i16 [[A]] to i32
67; CHECK-NEXT:    switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
68; CHECK-NEXT:      i32 37, label [[SW_BB:%.*]]
69; CHECK-NEXT:      i32 38, label [[SW_BB]]
70; CHECK-NEXT:      i32 39, label [[SW_BB]]
71; CHECK-NEXT:      i32 65537, label [[SW_BB]]
72; CHECK-NEXT:    ]
73; CHECK:       sw.bb:
74; CHECK-NEXT:    ret i1 [[B]]
75; CHECK:       sw.default:
76; CHECK-NEXT:    ret i1 [[C]]
77;
78entry:
79  %a.ext = zext i16 %a to i32
80  switch i32 %a.ext, label %sw.default [
81  i32 37, label %sw.bb
82  i32 38, label %sw.bb
83  i32 39, label %sw.bb
84  i32 65537, label %sw.bb
85  ]
86
87sw.bb:
88  ret i1 %b
89sw.default:
90  ret i1 %c
91}
92
93define i1 @test_switch_with_sext_unreachable_case(i16 %a, i1 %b, i1 %c) {
94; CHECK-LABEL: define i1 @test_switch_with_sext_unreachable_case(
95; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
96; CHECK-NEXT:  entry:
97; CHECK-NEXT:    [[A_EXT:%.*]] = sext i16 [[A]] to i32
98; CHECK-NEXT:    switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
99; CHECK-NEXT:      i32 37, label [[SW_BB:%.*]]
100; CHECK-NEXT:      i32 38, label [[SW_BB]]
101; CHECK-NEXT:      i32 39, label [[SW_BB]]
102; CHECK-NEXT:      i32 -65537, label [[SW_BB]]
103; CHECK-NEXT:    ]
104; CHECK:       sw.bb:
105; CHECK-NEXT:    ret i1 [[B]]
106; CHECK:       sw.default:
107; CHECK-NEXT:    ret i1 [[C]]
108;
109entry:
110  %a.ext = sext i16 %a to i32
111  switch i32 %a.ext, label %sw.default [
112  i32 37, label %sw.bb
113  i32 38, label %sw.bb
114  i32 39, label %sw.bb
115  i32 -65537, label %sw.bb
116  ]
117
118sw.bb:
119  ret i1 %b
120sw.default:
121  ret i1 %c
122}
123