1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -passes=instcombine < %s | FileCheck %s 3 4define i64 @test_shl_nuw_nsw__all_are_safe(i32 %x, i64 %y) { 5; CHECK-LABEL: @test_shl_nuw_nsw__all_are_safe( 6; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 7; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60 8; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 9; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 10; CHECK-NEXT: ret i64 [[TMP4]] 11; 12 %1 = and i32 %x, 15 13 %2 = shl nuw nsw i32 %1, 2 14 %3 = zext i32 %2 to i64 15 %4 = icmp eq i32 %1, 0 16 %5 = ashr i64 %y, %3 17 %6 = select i1 %4, i64 %y, i64 %5 18 ret i64 %6 19} 20 21define i64 @test_shl_nuw__all_are_safe(i32 %x, i64 %y) { 22; CHECK-LABEL: @test_shl_nuw__all_are_safe( 23; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 24; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60 25; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 26; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 27; CHECK-NEXT: ret i64 [[TMP4]] 28; 29 %1 = and i32 %x, 15 30 %2 = shl nuw i32 %1, 2 31 %3 = zext i32 %2 to i64 32 %4 = icmp eq i32 %1, 0 33 %5 = ashr i64 %y, %3 34 %6 = select i1 %4, i64 %y, i64 %5 35 ret i64 %6 36} 37 38define i64 @test_shl_nsw__all_are_safe(i32 %x, i64 %y) { 39; CHECK-LABEL: @test_shl_nsw__all_are_safe( 40; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 41; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60 42; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 43; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 44; CHECK-NEXT: ret i64 [[TMP4]] 45; 46 %1 = and i32 %x, 15 47 %2 = shl nsw i32 %1, 2 48 %3 = zext i32 %2 to i64 49 %4 = icmp eq i32 %1, 0 50 %5 = ashr i64 %y, %3 51 %6 = select i1 %4, i64 %y, i64 %5 52 ret i64 %6 53} 54 55define i64 @test_shl__all_are_safe(i32 %x, i64 %y) { 56; CHECK-LABEL: @test_shl__all_are_safe( 57; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 58; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 60 59; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 60; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 61; CHECK-NEXT: ret i64 [[TMP4]] 62; 63 %1 = and i32 %x, 15 64 %2 = shl i32 %1, 2 65 %3 = zext i32 %2 to i64 66 %4 = icmp eq i32 %1, 0 67 %5 = ashr i64 %y, %3 68 %6 = select i1 %4, i64 %y, i64 %5 69 ret i64 %6 70} 71 72define i64 @test_shl_nuw_nsw__nuw_is_safe(i32 %x, i64 %y) { 73; CHECK-LABEL: @test_shl_nuw_nsw__nuw_is_safe( 74; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 75; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 76; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 77; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 78; CHECK-NEXT: ret i64 [[TMP4]] 79; 80 %1 = and i32 %x, 1073741822 81 %2 = shl nuw nsw i32 %1, 2 82 %3 = zext i32 %2 to i64 83 %4 = icmp eq i32 %1, 0 84 %5 = ashr i64 %y, %3 85 %6 = select i1 %4, i64 %y, i64 %5 86 ret i64 %6 87} 88 89define i64 @test_shl_nuw__nuw_is_safe(i32 %x, i64 %y) { 90; CHECK-LABEL: @test_shl_nuw__nuw_is_safe( 91; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 92; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 93; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 94; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 95; CHECK-NEXT: ret i64 [[TMP4]] 96; 97 %1 = and i32 %x, 1073741822 98 %2 = shl nuw i32 %1, 2 99 %3 = zext i32 %2 to i64 100 %4 = icmp eq i32 %1, 0 101 %5 = ashr i64 %y, %3 102 %6 = select i1 %4, i64 %y, i64 %5 103 ret i64 %6 104} 105 106define i64 @test_shl_nsw__nuw_is_safe(i32 %x, i64 %y) { 107; CHECK-LABEL: @test_shl_nsw__nuw_is_safe( 108; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 109; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 110; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 111; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 112; CHECK-NEXT: ret i64 [[TMP4]] 113; 114 %1 = and i32 %x, 1073741822 115 %2 = shl nsw i32 %1, 2 116 %3 = zext i32 %2 to i64 117 %4 = icmp eq i32 %1, 0 118 %5 = ashr i64 %y, %3 119 %6 = select i1 %4, i64 %y, i64 %5 120 ret i64 %6 121} 122 123define i64 @test_shl__nuw_is_safe(i32 %x, i64 %y) { 124; CHECK-LABEL: @test_shl__nuw_is_safe( 125; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 126; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 127; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 128; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 129; CHECK-NEXT: ret i64 [[TMP4]] 130; 131 %1 = and i32 %x, 1073741822 132 %2 = shl i32 %1, 2 133 %3 = zext i32 %2 to i64 134 %4 = icmp eq i32 %1, 0 135 %5 = ashr i64 %y, %3 136 %6 = select i1 %4, i64 %y, i64 %5 137 ret i64 %6 138} 139 140define i32 @test_shl_nuw_nsw__nsw_is_safe(i32 %x) { 141; CHECK-LABEL: @test_shl_nuw_nsw__nsw_is_safe( 142; CHECK-NEXT: ret i32 0 143; 144 %1 = or i32 %x, -83886080 145 %2 = icmp eq i32 %1, -83886079 146 %3 = shl nuw nsw i32 %1, 2 147 %4 = select i1 %2, i32 -335544316, i32 %3 148 %5 = mul i32 %4, %1 149 %6 = mul i32 %5, %3 150 ret i32 %6 151} 152 153define i32 @test_shl_nuw__nsw_is_safe(i32 %x) { 154; CHECK-LABEL: @test_shl_nuw__nsw_is_safe( 155; CHECK-NEXT: ret i32 0 156; 157 %1 = or i32 %x, -83886080 158 %2 = icmp eq i32 %1, -83886079 159 %3 = shl nuw i32 %1, 2 160 %4 = select i1 %2, i32 -335544316, i32 %3 161 %5 = mul i32 %4, %1 162 %6 = mul i32 %5, %3 163 ret i32 %6 164} 165 166define i32 @test_shl_nsw__nsw_is_safe(i32 %x) { 167; CHECK-LABEL: @test_shl_nsw__nsw_is_safe( 168; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080 169; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2 170; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP1]] 171; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP2]] 172; CHECK-NEXT: ret i32 [[TMP4]] 173; 174 %1 = or i32 %x, -83886080 175 %2 = icmp eq i32 %1, -83886079 176 %3 = shl nsw i32 %1, 2 177 %4 = select i1 %2, i32 -335544316, i32 %3 178 %5 = mul i32 %4, %1 179 %6 = mul i32 %5, %3 180 ret i32 %6 181} 182 183define i32 @test_shl__nsw_is_safe(i32 %x) { 184; CHECK-LABEL: @test_shl__nsw_is_safe( 185; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[X:%.*]], -83886080 186; CHECK-NEXT: [[TMP2:%.*]] = shl nsw i32 [[TMP1]], 2 187; CHECK-NEXT: [[TMP3:%.*]] = mul i32 [[TMP2]], [[TMP1]] 188; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[TMP3]], [[TMP2]] 189; CHECK-NEXT: ret i32 [[TMP4]] 190; 191 %1 = or i32 %x, -83886080 192 %2 = icmp eq i32 %1, -83886079 193 %3 = shl i32 %1, 2 194 %4 = select i1 %2, i32 -335544316, i32 %3 195 %5 = mul i32 %4, %1 196 %6 = mul i32 %5, %3 197 ret i32 %6 198} 199 200 201define i64 @test_shl_nuw_nsw__none_are_safe(i32 %x, i64 %y) { 202; CHECK-LABEL: @test_shl_nuw_nsw__none_are_safe( 203; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 204; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 205; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 206; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 207; CHECK-NEXT: ret i64 [[TMP4]] 208; 209 %1 = and i32 %x, 4294967294 210 %2 = shl nuw nsw i32 %1, 2 211 %3 = zext i32 %2 to i64 212 %4 = icmp eq i32 %1, 0 213 %5 = ashr i64 %y, %3 214 %6 = select i1 %4, i64 %y, i64 %5 215 ret i64 %6 216} 217 218define i64 @test_shl_nuw__none_are_safe(i32 %x, i64 %y) { 219; CHECK-LABEL: @test_shl_nuw__none_are_safe( 220; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 221; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 222; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 223; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 224; CHECK-NEXT: ret i64 [[TMP4]] 225; 226 %1 = and i32 %x, 4294967294 227 %2 = shl nuw i32 %1, 2 228 %3 = zext i32 %2 to i64 229 %4 = icmp eq i32 %1, 0 230 %5 = ashr i64 %y, %3 231 %6 = select i1 %4, i64 %y, i64 %5 232 ret i64 %6 233} 234 235define i64 @test_shl_nsw__none_are_safe(i32 %x, i64 %y) { 236; CHECK-LABEL: @test_shl_nsw__none_are_safe( 237; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 238; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 239; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 240; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 241; CHECK-NEXT: ret i64 [[TMP4]] 242; 243 %1 = and i32 %x, 4294967294 244 %2 = shl nsw i32 %1, 2 245 %3 = zext i32 %2 to i64 246 %4 = icmp eq i32 %1, 0 247 %5 = ashr i64 %y, %3 248 %6 = select i1 %4, i64 %y, i64 %5 249 ret i64 %6 250} 251 252define i64 @test_shl__none_are_safe(i32 %x, i64 %y) { 253; CHECK-LABEL: @test_shl__none_are_safe( 254; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[X:%.*]], 2 255; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -8 256; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 257; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 258; CHECK-NEXT: ret i64 [[TMP4]] 259; 260 %1 = and i32 %x, 4294967294 261 %2 = shl i32 %1, 2 262 %3 = zext i32 %2 to i64 263 %4 = icmp eq i32 %1, 0 264 %5 = ashr i64 %y, %3 265 %6 = select i1 %4, i64 %y, i64 %5 266 ret i64 %6 267} 268 269define i64 @test_lshr_exact__exact_is_safe(i32 %x, i64 %y) { 270; CHECK-LABEL: @test_lshr_exact__exact_is_safe( 271; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2 272; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15 273; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 274; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 275; CHECK-NEXT: ret i64 [[TMP4]] 276; 277 %1 = and i32 %x, 60 278 %2 = lshr exact i32 %1, 2 279 %3 = zext i32 %2 to i64 280 %4 = icmp eq i32 %1, 0 281 %5 = ashr i64 %y, %3 282 %6 = select i1 %4, i64 %y, i64 %5 283 ret i64 %6 284} 285 286define i64 @test_lshr__exact_is_safe(i32 %x, i64 %y) { 287; CHECK-LABEL: @test_lshr__exact_is_safe( 288; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2 289; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15 290; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 291; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 292; CHECK-NEXT: ret i64 [[TMP4]] 293; 294 %1 = and i32 %x, 60 295 %2 = lshr i32 %1, 2 296 %3 = zext i32 %2 to i64 297 %4 = icmp eq i32 %1, 0 298 %5 = ashr i64 %y, %3 299 %6 = select i1 %4, i64 %y, i64 %5 300 ret i64 %6 301} 302 303define i64 @test_lshr_exact__exact_is_unsafe(i32 %x, i64 %y) { 304; CHECK-LABEL: @test_lshr_exact__exact_is_unsafe( 305; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2 306; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15 307; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 308; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 309; CHECK-NEXT: ret i64 [[TMP4]] 310; 311 %1 = and i32 %x, 63 312 %2 = lshr exact i32 %1, 2 313 %3 = zext i32 %2 to i64 314 %4 = icmp eq i32 %1, 0 315 %5 = ashr i64 %y, %3 316 %6 = select i1 %4, i64 %y, i64 %5 317 ret i64 %6 318} 319 320define i64 @test_lshr__exact_is_unsafe(i32 %x, i64 %y) { 321; CHECK-LABEL: @test_lshr__exact_is_unsafe( 322; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], 2 323; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 15 324; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 325; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 326; CHECK-NEXT: ret i64 [[TMP4]] 327; 328 %1 = and i32 %x, 63 329 %2 = lshr i32 %1, 2 330 %3 = zext i32 %2 to i64 331 %4 = icmp eq i32 %1, 0 332 %5 = ashr i64 %y, %3 333 %6 = select i1 %4, i64 %y, i64 %5 334 ret i64 %6 335} 336 337define i64 @test_ashr_exact__exact_is_safe(i32 %x, i64 %y) { 338; CHECK-LABEL: @test_ashr_exact__exact_is_safe( 339; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2 340; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897 341; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 342; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 343; CHECK-NEXT: ret i64 [[TMP4]] 344; 345 %1 = and i32 %x, -2147483588 346 %2 = ashr exact i32 %1, 2 347 %3 = zext i32 %2 to i64 348 %4 = icmp eq i32 %1, 0 349 %5 = ashr i64 %y, %3 350 %6 = select i1 %4, i64 %y, i64 %5 351 ret i64 %6 352} 353 354define i64 @test_ashr__exact_is_safe(i32 %x, i64 %y) { 355; CHECK-LABEL: @test_ashr__exact_is_safe( 356; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2 357; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897 358; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 359; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 360; CHECK-NEXT: ret i64 [[TMP4]] 361; 362 %1 = and i32 %x, -2147483588 363 %2 = ashr i32 %1, 2 364 %3 = zext i32 %2 to i64 365 %4 = icmp eq i32 %1, 0 366 %5 = ashr i64 %y, %3 367 %6 = select i1 %4, i64 %y, i64 %5 368 ret i64 %6 369} 370 371define i64 @test_ashr_exact__exact_is_unsafe(i32 %x, i64 %y) { 372; CHECK-LABEL: @test_ashr_exact__exact_is_unsafe( 373; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2 374; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897 375; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 376; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 377; CHECK-NEXT: ret i64 [[TMP4]] 378; 379 %1 = and i32 %x, -2147483585 380 %2 = ashr exact i32 %1, 2 381 %3 = zext i32 %2 to i64 382 %4 = icmp eq i32 %1, 0 383 %5 = ashr i64 %y, %3 384 %6 = select i1 %4, i64 %y, i64 %5 385 ret i64 %6 386} 387 388define i64 @test_ashr__exact_is_unsafe(i32 %x, i64 %y) { 389; CHECK-LABEL: @test_ashr__exact_is_unsafe( 390; CHECK-NEXT: [[TMP1:%.*]] = ashr i32 [[X:%.*]], 2 391; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], -536870897 392; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP2]] to i64 393; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[Y:%.*]], [[TMP3]] 394; CHECK-NEXT: ret i64 [[TMP4]] 395; 396 %1 = and i32 %x, -2147483585 397 %2 = ashr i32 %1, 2 398 %3 = zext i32 %2 to i64 399 %4 = icmp eq i32 %1, 0 400 %5 = ashr i64 %y, %3 401 %6 = select i1 %4, i64 %y, i64 %5 402 ret i64 %6 403} 404 405define i32 @test_add_nuw_nsw__all_are_safe(i32 %x) { 406; CHECK-LABEL: @test_add_nuw_nsw__all_are_safe( 407; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823 408; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1 409; CHECK-NEXT: ret i32 [[ADD]] 410; 411 %and = and i32 %x, 1073741823 412 %cmp = icmp eq i32 %and, 3 413 %add = add nuw nsw i32 %and, 1 414 %sel = select i1 %cmp, i32 4, i32 %add 415 ret i32 %sel 416} 417 418define i32 @test_add_nuw__all_are_safe(i32 %x) { 419; CHECK-LABEL: @test_add_nuw__all_are_safe( 420; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823 421; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1 422; CHECK-NEXT: ret i32 [[ADD]] 423; 424 %and = and i32 %x, 1073741823 425 %cmp = icmp eq i32 %and, 3 426 %add = add nuw i32 %and, 1 427 %sel = select i1 %cmp, i32 4, i32 %add 428 ret i32 %sel 429} 430 431define i32 @test_add_nsw__all_are_safe(i32 %x) { 432; CHECK-LABEL: @test_add_nsw__all_are_safe( 433; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823 434; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1 435; CHECK-NEXT: ret i32 [[ADD]] 436; 437 %and = and i32 %x, 1073741823 438 %cmp = icmp eq i32 %and, 3 439 %add = add nsw i32 %and, 1 440 %sel = select i1 %cmp, i32 4, i32 %add 441 ret i32 %sel 442} 443 444define i32 @test_add__all_are_safe(i32 %x) { 445; CHECK-LABEL: @test_add__all_are_safe( 446; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1073741823 447; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[AND]], 1 448; CHECK-NEXT: ret i32 [[ADD]] 449; 450 %and = and i32 %x, 1073741823 451 %cmp = icmp eq i32 %and, 3 452 %add = add i32 %and, 1 453 %sel = select i1 %cmp, i32 4, i32 %add 454 ret i32 %sel 455} 456 457define i32 @test_add_nuw_nsw__nuw_is_safe(i32 %x) { 458; CHECK-LABEL: @test_add_nuw_nsw__nuw_is_safe( 459; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 460; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[AND]], 1 461; CHECK-NEXT: ret i32 [[ADD]] 462; 463 %and = and i32 %x, 2147483647 464 %cmp = icmp eq i32 %and, 2147483647 465 %add = add nuw nsw i32 %and, 1 466 %sel = select i1 %cmp, i32 -2147483648, i32 %add 467 ret i32 %sel 468} 469 470define i32 @test_add_nuw__nuw_is_safe(i32 %x) { 471; CHECK-LABEL: @test_add_nuw__nuw_is_safe( 472; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 473; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[AND]], 1 474; CHECK-NEXT: ret i32 [[ADD]] 475; 476 %and = and i32 %x, 2147483647 477 %cmp = icmp eq i32 %and, 2147483647 478 %add = add nuw i32 %and, 1 479 %sel = select i1 %cmp, i32 -2147483648, i32 %add 480 ret i32 %sel 481} 482 483define i32 @test_add_nsw__nuw_is_safe(i32 %x) { 484; CHECK-LABEL: @test_add_nsw__nuw_is_safe( 485; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 486; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[AND]], 1 487; CHECK-NEXT: ret i32 [[ADD]] 488; 489 %and = and i32 %x, 2147483647 490 %cmp = icmp eq i32 %and, 2147483647 491 %add = add nsw i32 %and, 1 492 %sel = select i1 %cmp, i32 -2147483648, i32 %add 493 ret i32 %sel 494} 495 496define i32 @test_add__nuw_is_safe(i32 %x) { 497; CHECK-LABEL: @test_add__nuw_is_safe( 498; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 499; CHECK-NEXT: [[ADD:%.*]] = add nuw i32 [[AND]], 1 500; CHECK-NEXT: ret i32 [[ADD]] 501; 502 %and = and i32 %x, 2147483647 503 %cmp = icmp eq i32 %and, 2147483647 504 %add = add i32 %and, 1 505 %sel = select i1 %cmp, i32 -2147483648, i32 %add 506 ret i32 %sel 507} 508 509define i32 @test_add_nuw_nsw__nsw_is_safe(i32 %x) { 510; CHECK-LABEL: @test_add_nuw_nsw__nsw_is_safe( 511; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 512; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[OR]], 1 513; CHECK-NEXT: ret i32 [[ADD]] 514; 515 %or = or i32 %x, -2147483648 516 %cmp = icmp eq i32 %or, -1 517 %add = add nuw nsw i32 %or, 1 518 %sel = select i1 %cmp, i32 0, i32 %add 519 ret i32 %sel 520} 521 522define i32 @test_add_nuw__nsw_is_safe(i32 %x) { 523; CHECK-LABEL: @test_add_nuw__nsw_is_safe( 524; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 525; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[OR]], 1 526; CHECK-NEXT: ret i32 [[ADD]] 527; 528 %or = or i32 %x, -2147483648 529 %cmp = icmp eq i32 %or, -1 530 %add = add nuw i32 %or, 1 531 %sel = select i1 %cmp, i32 0, i32 %add 532 ret i32 %sel 533} 534 535define i32 @test_add_nsw__nsw_is_safe(i32 %x) { 536; CHECK-LABEL: @test_add_nsw__nsw_is_safe( 537; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 538; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[OR]], 1 539; CHECK-NEXT: ret i32 [[ADD]] 540; 541 %or = or i32 %x, -2147483648 542 %cmp = icmp eq i32 %or, -1 543 %add = add nsw i32 %or, 1 544 %sel = select i1 %cmp, i32 0, i32 %add 545 ret i32 %sel 546} 547 548define i32 @test_add__nsw_is_safe(i32 %x) { 549; CHECK-LABEL: @test_add__nsw_is_safe( 550; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 551; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[OR]], 1 552; CHECK-NEXT: ret i32 [[ADD]] 553; 554 %or = or i32 %x, -2147483648 555 %cmp = icmp eq i32 %or, -1 556 %add = add i32 %or, 1 557 %sel = select i1 %cmp, i32 0, i32 %add 558 ret i32 %sel 559} 560 561define i32 @test_add_nuw_nsw__none_are_safe(i32 %x) { 562; CHECK-LABEL: @test_add_nuw_nsw__none_are_safe( 563; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1 564; CHECK-NEXT: ret i32 [[ADD]] 565; 566 %cmp = icmp eq i32 %x, 3 567 %add = add nuw nsw i32 %x, 1 568 %sel = select i1 %cmp, i32 4, i32 %add 569 ret i32 %sel 570} 571 572define i32 @test_add_nuw__none_are_safe(i32 %x) { 573; CHECK-LABEL: @test_add_nuw__none_are_safe( 574; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1 575; CHECK-NEXT: ret i32 [[ADD]] 576; 577 %cmp = icmp eq i32 %x, 3 578 %add = add nuw i32 %x, 1 579 %sel = select i1 %cmp, i32 4, i32 %add 580 ret i32 %sel 581} 582 583define i32 @test_add_nsw__none_are_safe(i32 %x) { 584; CHECK-LABEL: @test_add_nsw__none_are_safe( 585; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1 586; CHECK-NEXT: ret i32 [[ADD]] 587; 588 %cmp = icmp eq i32 %x, 3 589 %add = add nsw i32 %x, 1 590 %sel = select i1 %cmp, i32 4, i32 %add 591 ret i32 %sel 592} 593 594define i32 @test_add__none_are_safe(i32 %x) { 595; CHECK-LABEL: @test_add__none_are_safe( 596; CHECK-NEXT: [[ADD:%.*]] = add i32 [[X:%.*]], 1 597; CHECK-NEXT: ret i32 [[ADD]] 598; 599 %cmp = icmp eq i32 %x, 3 600 %add = add i32 %x, 1 601 %sel = select i1 %cmp, i32 4, i32 %add 602 ret i32 %sel 603} 604 605define i32 @test_sub_nuw_nsw__all_are_safe(i32 %x) { 606; CHECK-LABEL: @test_sub_nuw_nsw__all_are_safe( 607; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 608; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]] 609; CHECK-NEXT: ret i32 [[SUB]] 610; 611 %and = and i32 %x, 255 612 %cmp = icmp eq i32 %and, 6 613 %sub = sub nuw nsw i32 -254, %and 614 %sel = select i1 %cmp, i32 -260, i32 %sub 615 ret i32 %sel 616} 617 618define i32 @test_sub_nuw__all_are_safe(i32 %x) { 619; CHECK-LABEL: @test_sub_nuw__all_are_safe( 620; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 621; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]] 622; CHECK-NEXT: ret i32 [[SUB]] 623; 624 %and = and i32 %x, 255 625 %cmp = icmp eq i32 %and, 6 626 %sub = sub nuw i32 -254, %and 627 %sel = select i1 %cmp, i32 -260, i32 %sub 628 ret i32 %sel 629} 630 631define i32 @test_sub_nsw__all_are_safe(i32 %x) { 632; CHECK-LABEL: @test_sub_nsw__all_are_safe( 633; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 634; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]] 635; CHECK-NEXT: ret i32 [[SUB]] 636; 637 %and = and i32 %x, 255 638 %cmp = icmp eq i32 %and, 6 639 %sub = sub nsw i32 -254, %and 640 %sel = select i1 %cmp, i32 -260, i32 %sub 641 ret i32 %sel 642} 643 644define i32 @test_sub__all_are_safe(i32 %x) { 645; CHECK-LABEL: @test_sub__all_are_safe( 646; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 647; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 -254, [[AND]] 648; CHECK-NEXT: ret i32 [[SUB]] 649; 650 %and = and i32 %x, 255 651 %cmp = icmp eq i32 %and, 6 652 %sub = sub i32 -254, %and 653 %sel = select i1 %cmp, i32 -260, i32 %sub 654 ret i32 %sel 655} 656 657define i32 @test_sub_nuw_nsw__nuw_is_safe(i32 %x) { 658; CHECK-LABEL: @test_sub_nuw_nsw__nuw_is_safe( 659; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 660; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]] 661; CHECK-NEXT: ret i32 [[SUB]] 662; 663 %and = and i32 %x, 2147483647 664 %cmp = icmp eq i32 %and, 1073741824 665 %sub = sub nuw nsw i32 -2147483648, %and 666 %sel = select i1 %cmp, i32 1073741824, i32 %sub 667 ret i32 %sel 668} 669 670define i32 @test_sub_nuw__nuw_is_safe(i32 %x) { 671; CHECK-LABEL: @test_sub_nuw__nuw_is_safe( 672; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 673; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]] 674; CHECK-NEXT: ret i32 [[SUB]] 675; 676 %and = and i32 %x, 2147483647 677 %cmp = icmp eq i32 %and, 1073741824 678 %sub = sub nuw i32 -2147483648, %and 679 %sel = select i1 %cmp, i32 1073741824, i32 %sub 680 ret i32 %sel 681} 682 683define i32 @test_sub_nsw__nuw_is_safe(i32 %x) { 684; CHECK-LABEL: @test_sub_nsw__nuw_is_safe( 685; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 686; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]] 687; CHECK-NEXT: ret i32 [[SUB]] 688; 689 %and = and i32 %x, 2147483647 690 %cmp = icmp eq i32 %and, 1073741824 691 %sub = sub nsw i32 -2147483648, %and 692 %sel = select i1 %cmp, i32 1073741824, i32 %sub 693 ret i32 %sel 694} 695 696define i32 @test_sub__nuw_is_safe(i32 %x) { 697; CHECK-LABEL: @test_sub__nuw_is_safe( 698; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 2147483647 699; CHECK-NEXT: [[SUB:%.*]] = sub nuw i32 -2147483648, [[AND]] 700; CHECK-NEXT: ret i32 [[SUB]] 701; 702 %and = and i32 %x, 2147483647 703 %cmp = icmp eq i32 %and, 1073741824 704 %sub = sub i32 -2147483648, %and 705 %sel = select i1 %cmp, i32 1073741824, i32 %sub 706 ret i32 %sel 707} 708 709define i32 @test_sub_nuw_nsw__nsw_is_safe(i32 %x) { 710; CHECK-LABEL: @test_sub_nuw_nsw__nsw_is_safe( 711; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 712; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]] 713; CHECK-NEXT: ret i32 [[SUB]] 714; 715 %or = or i32 %x, -2147483648 716 %cmp = icmp eq i32 %or, -2147483647 717 %sub = sub nuw nsw i32 -2147483648, %or 718 %sel = select i1 %cmp, i32 -1, i32 %sub 719 ret i32 %sel 720} 721 722define i32 @test_sub_nuw__nsw_is_safe(i32 %x) { 723; CHECK-LABEL: @test_sub_nuw__nsw_is_safe( 724; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 725; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]] 726; CHECK-NEXT: ret i32 [[SUB]] 727; 728 %or = or i32 %x, -2147483648 729 %cmp = icmp eq i32 %or, -2147483647 730 %sub = sub nuw i32 -2147483648, %or 731 %sel = select i1 %cmp, i32 -1, i32 %sub 732 ret i32 %sel 733} 734 735define i32 @test_sub_nsw__nsw_is_safe(i32 %x) { 736; CHECK-LABEL: @test_sub_nsw__nsw_is_safe( 737; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 738; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]] 739; CHECK-NEXT: ret i32 [[SUB]] 740; 741 %or = or i32 %x, -2147483648 742 %cmp = icmp eq i32 %or, -2147483647 743 %sub = sub nsw i32 -2147483648, %or 744 %sel = select i1 %cmp, i32 -1, i32 %sub 745 ret i32 %sel 746} 747 748define i32 @test_sub__nsw_is_safe(i32 %x) { 749; CHECK-LABEL: @test_sub__nsw_is_safe( 750; CHECK-NEXT: [[OR:%.*]] = or i32 [[X:%.*]], -2147483648 751; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 -2147483648, [[OR]] 752; CHECK-NEXT: ret i32 [[SUB]] 753; 754 %or = or i32 %x, -2147483648 755 %cmp = icmp eq i32 %or, -2147483647 756 %sub = sub i32 -2147483648, %or 757 %sel = select i1 %cmp, i32 -1, i32 %sub 758 ret i32 %sel 759} 760 761define i32 @test_sub_nuw_nsw__none_are_safe(i32 %x) { 762; CHECK-LABEL: @test_sub_nuw_nsw__none_are_safe( 763; CHECK-NEXT: [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]] 764; CHECK-NEXT: ret i32 [[SUB]] 765; 766 %cmp = icmp eq i32 %x, 1 767 %sub = sub nuw nsw i32 -2147483648, %x 768 %sel = select i1 %cmp, i32 2147483647, i32 %sub 769 ret i32 %sel 770} 771 772define i32 @test_sub_nuw__none_are_safe(i32 %x) { 773; CHECK-LABEL: @test_sub_nuw__none_are_safe( 774; CHECK-NEXT: [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]] 775; CHECK-NEXT: ret i32 [[SUB]] 776; 777 %cmp = icmp eq i32 %x, 1 778 %sub = sub nuw i32 -2147483648, %x 779 %sel = select i1 %cmp, i32 2147483647, i32 %sub 780 ret i32 %sel 781} 782 783define i32 @test_sub_nsw__none_are_safe(i32 %x) { 784; CHECK-LABEL: @test_sub_nsw__none_are_safe( 785; CHECK-NEXT: [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]] 786; CHECK-NEXT: ret i32 [[SUB]] 787; 788 %cmp = icmp eq i32 %x, 1 789 %sub = sub nsw i32 -2147483648, %x 790 %sel = select i1 %cmp, i32 2147483647, i32 %sub 791 ret i32 %sel 792} 793 794define i32 @test_sub__none_are_safe(i32 %x) { 795; CHECK-LABEL: @test_sub__none_are_safe( 796; CHECK-NEXT: [[SUB:%.*]] = sub i32 -2147483648, [[X:%.*]] 797; CHECK-NEXT: ret i32 [[SUB]] 798; 799 %cmp = icmp eq i32 %x, 1 800 %sub = sub i32 -2147483648, %x 801 %sel = select i1 %cmp, i32 2147483647, i32 %sub 802 ret i32 %sel 803} 804 805define i32 @test_mul_nuw_nsw__all_are_safe(i32 %x) { 806; CHECK-LABEL: @test_mul_nuw_nsw__all_are_safe( 807; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 808; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9 809; CHECK-NEXT: ret i32 [[MUL]] 810; 811 %and = and i32 %x, 255 812 %cmp = icmp eq i32 %and, 17 813 %mul = mul nuw nsw i32 %and, 9 814 %sel = select i1 %cmp, i32 153, i32 %mul 815 ret i32 %sel 816} 817 818define i32 @test_mul_nuw__all_are_safe(i32 %x) { 819; CHECK-LABEL: @test_mul_nuw__all_are_safe( 820; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 821; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9 822; CHECK-NEXT: ret i32 [[MUL]] 823; 824 %and = and i32 %x, 255 825 %cmp = icmp eq i32 %and, 17 826 %mul = mul nuw i32 %and, 9 827 %sel = select i1 %cmp, i32 153, i32 %mul 828 ret i32 %sel 829} 830 831define i32 @test_mul_nsw__all_are_safe(i32 %x) { 832; CHECK-LABEL: @test_mul_nsw__all_are_safe( 833; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 834; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9 835; CHECK-NEXT: ret i32 [[MUL]] 836; 837 %and = and i32 %x, 255 838 %cmp = icmp eq i32 %and, 17 839 %mul = mul nsw i32 %and, 9 840 %sel = select i1 %cmp, i32 153, i32 %mul 841 ret i32 %sel 842} 843 844define i32 @test_mul__all_are_safe(i32 %x) { 845; CHECK-LABEL: @test_mul__all_are_safe( 846; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 255 847; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i32 [[AND]], 9 848; CHECK-NEXT: ret i32 [[MUL]] 849; 850 %and = and i32 %x, 255 851 %cmp = icmp eq i32 %and, 17 852 %mul = mul i32 %and, 9 853 %sel = select i1 %cmp, i32 153, i32 %mul 854 ret i32 %sel 855} 856 857define i32 @test_mul_nuw_nsw__nuw_is_safe(i32 %x) { 858; CHECK-LABEL: @test_mul_nuw_nsw__nuw_is_safe( 859; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457 860; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[AND]], 9 861; CHECK-NEXT: ret i32 [[MUL]] 862; 863 %and = and i32 %x, 268435457 864 %cmp = icmp eq i32 %and, 268435456 865 %mul = mul nuw nsw i32 %and, 9 866 %sel = select i1 %cmp, i32 -1879048192, i32 %mul 867 ret i32 %sel 868} 869 870define i32 @test_mul_nuw__nuw_is_safe(i32 %x) { 871; CHECK-LABEL: @test_mul_nuw__nuw_is_safe( 872; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457 873; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[AND]], 9 874; CHECK-NEXT: ret i32 [[MUL]] 875; 876 %and = and i32 %x, 268435457 877 %cmp = icmp eq i32 %and, 268435456 878 %mul = mul nuw i32 %and, 9 879 %sel = select i1 %cmp, i32 -1879048192, i32 %mul 880 ret i32 %sel 881} 882 883define i32 @test_mul_nsw__nuw_is_safe(i32 %x) { 884; CHECK-LABEL: @test_mul_nsw__nuw_is_safe( 885; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457 886; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[AND]], 9 887; CHECK-NEXT: ret i32 [[MUL]] 888; 889 %and = and i32 %x, 268435457 890 %cmp = icmp eq i32 %and, 268435456 891 %mul = mul nsw i32 %and, 9 892 %sel = select i1 %cmp, i32 -1879048192, i32 %mul 893 ret i32 %sel 894} 895 896define i32 @test_mul__nuw_is_safe(i32 %x) { 897; CHECK-LABEL: @test_mul__nuw_is_safe( 898; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 268435457 899; CHECK-NEXT: [[MUL:%.*]] = mul nuw i32 [[AND]], 9 900; CHECK-NEXT: ret i32 [[MUL]] 901; 902 %and = and i32 %x, 268435457 903 %cmp = icmp eq i32 %and, 268435456 904 %mul = mul i32 %and, 9 905 %sel = select i1 %cmp, i32 -1879048192, i32 %mul 906 ret i32 %sel 907} 908 909define i32 @test_mul_nuw_nsw__nsw_is_safe(i32 %x) { 910; CHECK-LABEL: @test_mul_nuw_nsw__nsw_is_safe( 911; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080 912; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[AND]], 9 913; CHECK-NEXT: ret i32 [[MUL]] 914; 915 %and = or i32 %x, -83886080 916 %cmp = icmp eq i32 %and, -83886079 917 %mul = mul nuw nsw i32 %and, 9 918 %sel = select i1 %cmp, i32 -754974711, i32 %mul 919 ret i32 %sel 920} 921 922define i32 @test_mul_nuw__nsw_is_safe(i32 %x) { 923; CHECK-LABEL: @test_mul_nuw__nsw_is_safe( 924; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080 925; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[AND]], 9 926; CHECK-NEXT: ret i32 [[MUL]] 927; 928 %and = or i32 %x, -83886080 929 %cmp = icmp eq i32 %and, -83886079 930 %mul = mul nuw i32 %and, 9 931 %sel = select i1 %cmp, i32 -754974711, i32 %mul 932 ret i32 %sel 933} 934 935define i32 @test_mul_nsw__nsw_is_safe(i32 %x) { 936; CHECK-LABEL: @test_mul_nsw__nsw_is_safe( 937; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080 938; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[AND]], 9 939; CHECK-NEXT: ret i32 [[MUL]] 940; 941 %and = or i32 %x, -83886080 942 %cmp = icmp eq i32 %and, -83886079 943 %mul = mul nsw i32 %and, 9 944 %sel = select i1 %cmp, i32 -754974711, i32 %mul 945 ret i32 %sel 946} 947 948define i32 @test_mul__nsw_is_safe(i32 %x) { 949; CHECK-LABEL: @test_mul__nsw_is_safe( 950; CHECK-NEXT: [[AND:%.*]] = or i32 [[X:%.*]], -83886080 951; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[AND]], 9 952; CHECK-NEXT: ret i32 [[MUL]] 953; 954 %and = or i32 %x, -83886080 955 %cmp = icmp eq i32 %and, -83886079 956 %mul = mul i32 %and, 9 957 %sel = select i1 %cmp, i32 -754974711, i32 %mul 958 ret i32 %sel 959} 960 961define i32 @test_mul_nuw_nsw__none_are_safe(i32 %x) { 962; CHECK-LABEL: @test_mul_nuw_nsw__none_are_safe( 963; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 9 964; CHECK-NEXT: ret i32 [[MUL]] 965; 966 %cmp = icmp eq i32 %x, 805306368 967 %mul = mul nuw nsw i32 %x, 9 968 %sel = select i1 %cmp, i32 -1342177280, i32 %mul 969 ret i32 %sel 970} 971 972define i32 @test_mul_nuw__none_are_safe(i32 %x) { 973; CHECK-LABEL: @test_mul_nuw__none_are_safe( 974; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 9 975; CHECK-NEXT: ret i32 [[MUL]] 976; 977 %cmp = icmp eq i32 %x, 805306368 978 %mul = mul nuw i32 %x, 9 979 %sel = select i1 %cmp, i32 -1342177280, i32 %mul 980 ret i32 %sel 981} 982 983define i32 @test_mul_nsw__none_are_safe(i32 %x) { 984; CHECK-LABEL: @test_mul_nsw__none_are_safe( 985; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 9 986; CHECK-NEXT: ret i32 [[MUL]] 987; 988 %cmp = icmp eq i32 %x, 805306368 989 %mul = mul nsw i32 %x, 9 990 %sel = select i1 %cmp, i32 -1342177280, i32 %mul 991 ret i32 %sel 992} 993 994define i32 @test_mul__none_are_safe(i32 %x) { 995; CHECK-LABEL: @test_mul__none_are_safe( 996; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[X:%.*]], 9 997; CHECK-NEXT: ret i32 [[MUL]] 998; 999 %cmp = icmp eq i32 %x, 805306368 1000 %mul = mul i32 %x, 9 1001 %sel = select i1 %cmp, i32 -1342177280, i32 %mul 1002 ret i32 %sel 1003} 1004