xref: /llvm-project/llvm/test/Transforms/InstCombine/reduction-mul-sext-zext-i1.ll (revision 2caaec65c04ea7d0e9568b7895b7a46d6100cb75)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=instcombine -S | FileCheck %s
3
4define i1 @reduce_mul_self(<8 x i1> %x) {
5; CHECK-LABEL: @reduce_mul_self(
6; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
7; CHECK-NEXT:    [[RES:%.*]] = icmp eq i8 [[TMP1]], -1
8; CHECK-NEXT:    ret i1 [[RES]]
9;
10  %res = call i1 @llvm.vector.reduce.mul.v8i32(<8 x i1> %x)
11  ret i1 %res
12}
13
14define i32 @reduce_mul_sext(<4 x i1> %x) {
15; CHECK-LABEL: @reduce_mul_sext(
16; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
17; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1
18; CHECK-NEXT:    [[RES:%.*]] = zext i1 [[TMP2]] to i32
19; CHECK-NEXT:    ret i32 [[RES]]
20;
21  %sext = sext <4 x i1> %x to <4 x i32>
22  %res = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %sext)
23  ret i32 %res
24}
25
26define i64 @reduce_mul_zext(<8 x i1> %x) {
27; CHECK-LABEL: @reduce_mul_zext(
28; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
29; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
30; CHECK-NEXT:    [[RES:%.*]] = zext i1 [[TMP2]] to i64
31; CHECK-NEXT:    ret i64 [[RES]]
32;
33  %zext = zext <8 x i1> %x to <8 x i64>
34  %res = call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> %zext)
35  ret i64 %res
36}
37
38define i16 @reduce_mul_sext_same(<16 x i1> %x) {
39; CHECK-LABEL: @reduce_mul_sext_same(
40; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i16
41; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i16 [[TMP1]], -1
42; CHECK-NEXT:    [[RES:%.*]] = zext i1 [[TMP2]] to i16
43; CHECK-NEXT:    ret i16 [[RES]]
44;
45  %sext = sext <16 x i1> %x to <16 x i16>
46  %res = call i16 @llvm.vector.reduce.mul.v16i16(<16 x i16> %sext)
47  ret i16 %res
48}
49
50define i8 @reduce_mul_zext_long(<128 x i1> %x) {
51; CHECK-LABEL: @reduce_mul_zext_long(
52; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
53; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i128 [[TMP1]], -1
54; CHECK-NEXT:    [[RES:%.*]] = zext i1 [[TMP2]] to i8
55; CHECK-NEXT:    ret i8 [[RES]]
56;
57  %sext = sext <128 x i1> %x to <128 x i8>
58  %res = call i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> %sext)
59  ret i8 %res
60}
61
62@glob = external global i8, align 1
63define i8 @reduce_mul_zext_long_external_use(<128 x i1> %x) {
64; CHECK-LABEL: @reduce_mul_zext_long_external_use(
65; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
66; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i128 [[TMP1]], -1
67; CHECK-NEXT:    [[RES:%.*]] = zext i1 [[TMP2]] to i8
68; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <128 x i1> [[X]], i64 0
69; CHECK-NEXT:    [[EXT:%.*]] = sext i1 [[TMP3]] to i8
70; CHECK-NEXT:    store i8 [[EXT]], ptr @glob, align 1
71; CHECK-NEXT:    ret i8 [[RES]]
72;
73  %sext = sext <128 x i1> %x to <128 x i8>
74  %res = call i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> %sext)
75  %ext = extractelement <128 x i8> %sext, i32 0
76  store i8 %ext, ptr @glob, align 1
77  ret i8 %res
78}
79
80@glob1 = external global i64, align 8
81define i64 @reduce_mul_zext_external_use(<8 x i1> %x) {
82; CHECK-LABEL: @reduce_mul_zext_external_use(
83; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
84; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i8 [[TMP1]], -1
85; CHECK-NEXT:    [[RES:%.*]] = zext i1 [[TMP2]] to i64
86; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <8 x i1> [[X]], i64 0
87; CHECK-NEXT:    [[EXT:%.*]] = zext i1 [[TMP3]] to i64
88; CHECK-NEXT:    store i64 [[EXT]], ptr @glob1, align 8
89; CHECK-NEXT:    ret i64 [[RES]]
90;
91  %zext = zext <8 x i1> %x to <8 x i64>
92  %res = call i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> %zext)
93  %ext = extractelement <8 x i64> %zext, i32 0
94  store i64 %ext, ptr @glob1, align 8
95  ret i64 %res
96}
97
98declare i1 @llvm.vector.reduce.mul.v8i32(<8 x i1> %a)
99declare i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %a)
100declare i64 @llvm.vector.reduce.mul.v8i64(<8 x i64> %a)
101declare i16 @llvm.vector.reduce.mul.v16i16(<16 x i16> %a)
102declare i8 @llvm.vector.reduce.mul.v128i8(<128 x i8> %a)
103