1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -passes=instcombine -S < %s | FileCheck %s 3 4define i64 @test_or(i64 %a) { 5; CHECK-LABEL: @test_or( 6; CHECK-NEXT: entry: 7; CHECK-NEXT: [[TMP0:%.*]] = or i64 [[A:%.*]], 15 8; CHECK-NEXT: br label [[LOOP:%.*]] 9; CHECK: loop: 10; CHECK-NEXT: tail call void @use(i64 [[TMP0]]) 11; CHECK-NEXT: br label [[LOOP]] 12; 13entry: 14 br label %loop 15 16loop: ; preds = %loop, %entry 17 %iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ] 18 %iv.next = or i64 %iv, 15 19 tail call void @use(i64 %iv.next) 20 br label %loop 21} 22 23 24define i64 @test_or2(i64 %a, i64 %b) { 25; CHECK-LABEL: @test_or2( 26; CHECK-NEXT: entry: 27; CHECK-NEXT: br label [[LOOP:%.*]] 28; CHECK: loop: 29; CHECK-NEXT: [[IV_NEXT:%.*]] = or i64 [[A:%.*]], [[B:%.*]] 30; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]]) 31; CHECK-NEXT: br label [[LOOP]] 32; 33entry: 34 br label %loop 35 36loop: ; preds = %loop, %entry 37 %iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ] 38 %iv.next = or i64 %iv, %b 39 tail call void @use(i64 %iv.next) 40 br label %loop 41} 42 43define i64 @test_or3(i64 %a, i64 %b) { 44; CHECK-LABEL: @test_or3( 45; CHECK-NEXT: entry: 46; CHECK-NEXT: br label [[LOOP:%.*]] 47; CHECK: loop: 48; CHECK-NEXT: [[IV_NEXT:%.*]] = or i64 [[A:%.*]], [[B:%.*]] 49; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]]) 50; CHECK-NEXT: br label [[LOOP]] 51; 52entry: 53 br label %loop 54 55loop: ; preds = %loop, %entry 56 %iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ] 57 %iv.next = or i64 %b, %iv 58 tail call void @use(i64 %iv.next) 59 br label %loop 60} 61 62define i64 @test_or4(i64 %a, ptr %p) { 63; CHECK-LABEL: @test_or4( 64; CHECK-NEXT: entry: 65; CHECK-NEXT: br label [[LOOP:%.*]] 66; CHECK: loop: 67; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[A:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] 68; CHECK-NEXT: [[STEP:%.*]] = load volatile i64, ptr [[P:%.*]], align 4 69; CHECK-NEXT: [[IV_NEXT]] = or i64 [[IV]], [[STEP]] 70; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]]) 71; CHECK-NEXT: br label [[LOOP]] 72; 73entry: 74 br label %loop 75 76loop: ; preds = %loop, %entry 77 %iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ] 78 %step = load volatile i64, ptr %p 79 %iv.next = or i64 %iv, %step 80 tail call void @use(i64 %iv.next) 81 br label %loop 82} 83 84define i64 @test_and(i64 %a) { 85; CHECK-LABEL: @test_and( 86; CHECK-NEXT: entry: 87; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[A:%.*]], 15 88; CHECK-NEXT: br label [[LOOP:%.*]] 89; CHECK: loop: 90; CHECK-NEXT: tail call void @use(i64 [[TMP0]]) 91; CHECK-NEXT: br label [[LOOP]] 92; 93entry: 94 br label %loop 95 96loop: ; preds = %loop, %entry 97 %iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ] 98 %iv.next = and i64 %iv, 15 99 tail call void @use(i64 %iv.next) 100 br label %loop 101} 102 103 104define i64 @test_and2(i64 %a, i64 %b) { 105; CHECK-LABEL: @test_and2( 106; CHECK-NEXT: entry: 107; CHECK-NEXT: br label [[LOOP:%.*]] 108; CHECK: loop: 109; CHECK-NEXT: [[IV_NEXT:%.*]] = and i64 [[A:%.*]], [[B:%.*]] 110; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]]) 111; CHECK-NEXT: br label [[LOOP]] 112; 113entry: 114 br label %loop 115 116loop: ; preds = %loop, %entry 117 %iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ] 118 %iv.next = and i64 %iv, %b 119 tail call void @use(i64 %iv.next) 120 br label %loop 121} 122 123define i64 @test_and3(i64 %a, i64 %b) { 124; CHECK-LABEL: @test_and3( 125; CHECK-NEXT: entry: 126; CHECK-NEXT: br label [[LOOP:%.*]] 127; CHECK: loop: 128; CHECK-NEXT: [[IV_NEXT:%.*]] = and i64 [[A:%.*]], [[B:%.*]] 129; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]]) 130; CHECK-NEXT: br label [[LOOP]] 131; 132entry: 133 br label %loop 134 135loop: ; preds = %loop, %entry 136 %iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ] 137 %iv.next = and i64 %b, %iv 138 tail call void @use(i64 %iv.next) 139 br label %loop 140} 141 142 143define i64 @test_and4(i64 %a, ptr %p) { 144; CHECK-LABEL: @test_and4( 145; CHECK-NEXT: entry: 146; CHECK-NEXT: br label [[LOOP:%.*]] 147; CHECK: loop: 148; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[A:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] 149; CHECK-NEXT: [[STEP:%.*]] = load volatile i64, ptr [[P:%.*]], align 4 150; CHECK-NEXT: [[IV_NEXT]] = and i64 [[IV]], [[STEP]] 151; CHECK-NEXT: tail call void @use(i64 [[IV_NEXT]]) 152; CHECK-NEXT: br label [[LOOP]] 153; 154entry: 155 br label %loop 156 157loop: ; preds = %loop, %entry 158 %iv = phi i64 [ %a, %entry ], [ %iv.next, %loop ] 159 %step = load volatile i64, ptr %p 160 %iv.next = and i64 %iv, %step 161 tail call void @use(i64 %iv.next) 162 br label %loop 163} 164 165declare void @use(i64) 166