xref: /llvm-project/llvm/test/Transforms/InstCombine/pr80597.ll (revision 154c8a02ed952fe3fa2e074fce52a07c4d1efab2)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2; RUN: opt -S -passes=instcombine < %s | FileCheck %s
3
4define i64 @pr80597(i1 %cond) {
5; CHECK-LABEL: define i64 @pr80597(
6; CHECK-SAME: i1 [[COND:%.*]]) {
7; CHECK-NEXT:  entry:
8; CHECK-NEXT:    [[ADD:%.*]] = select i1 [[COND]], i64 0, i64 -12884901888
9; CHECK-NEXT:    [[SEXT1:%.*]] = add nsw i64 [[ADD]], 8836839514384105472
10; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i64 [[SEXT1]], -34359738368
11; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
12; CHECK:       if.else:
13; CHECK-NEXT:    [[SEXT2:%.*]] = ashr exact i64 [[ADD]], 1
14; CHECK-NEXT:    [[ASHR:%.*]] = or disjoint i64 [[SEXT2]], 4418419761487020032
15; CHECK-NEXT:    ret i64 [[ASHR]]
16; CHECK:       if.then:
17; CHECK-NEXT:    ret i64 0
18;
19entry:
20  %add = select i1 %cond, i64 0, i64 4294967293
21  %add8 = shl i64 %add, 32
22  %sext1 = add i64 %add8, 8836839514384105472
23  %cmp = icmp ult i64 %sext1, -34359738368
24  br i1 %cmp, label %if.then, label %if.else
25
26if.else:
27  %sext2 = or i64 %add8, 8836839522974040064
28  %ashr = ashr i64 %sext2, 1
29  ret i64 %ashr
30
31if.then:
32  ret i64 0
33}
34