1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -passes=instcombine < %s | FileCheck %s 3 4target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" 5target triple = "x86_64-pc-linux-gnu" 6 7@a = dso_local local_unnamed_addr global i64 0, align 8 8@d = dso_local local_unnamed_addr global i64 0, align 8 9@c = external dso_local local_unnamed_addr global i8, align 1 10 11define void @test(ptr nocapture readonly %arg) local_unnamed_addr { 12; CHECK-LABEL: @test( 13; CHECK-NEXT: bb: 14; CHECK-NEXT: [[I:%.*]] = load i64, ptr @d, align 8 15; CHECK-NEXT: [[I1:%.*]] = icmp eq i64 [[I]], 0 16; CHECK-NEXT: [[I2:%.*]] = load i64, ptr @a, align 8 17; CHECK-NEXT: [[I3:%.*]] = icmp ne i64 [[I2]], 0 18; CHECK-NEXT: br i1 [[I1]], label [[BB13:%.*]], label [[BB4:%.*]] 19; CHECK: bb4: 20; CHECK-NEXT: [[I5:%.*]] = load i16, ptr [[ARG:%.*]], align 2 21; CHECK-NEXT: [[I6:%.*]] = trunc i16 [[I5]] to i8 22; CHECK-NEXT: store i8 [[I6]], ptr @c, align 1 23; CHECK-NEXT: tail call void @llvm.assume(i1 [[I3]]) 24; CHECK-NEXT: br label [[BB22:%.*]] 25; CHECK: bb13: 26; CHECK-NEXT: [[I14:%.*]] = load i16, ptr [[ARG]], align 2 27; CHECK-NEXT: [[I15:%.*]] = trunc i16 [[I14]] to i8 28; CHECK-NEXT: store i8 [[I15]], ptr @c, align 1 29; CHECK-NEXT: br label [[BB22]] 30; CHECK: bb22: 31; CHECK-NEXT: [[STOREMERGE2_IN:%.*]] = load i16, ptr [[ARG]], align 2 32; CHECK-NEXT: [[STOREMERGE2:%.*]] = trunc i16 [[STOREMERGE2_IN]] to i8 33; CHECK-NEXT: store i8 [[STOREMERGE2]], ptr @c, align 1 34; CHECK-NEXT: [[STOREMERGE1_IN:%.*]] = load i16, ptr [[ARG]], align 2 35; CHECK-NEXT: [[STOREMERGE1:%.*]] = trunc i16 [[STOREMERGE1_IN]] to i8 36; CHECK-NEXT: store i8 [[STOREMERGE1]], ptr @c, align 1 37; CHECK-NEXT: [[STOREMERGE_IN:%.*]] = load i16, ptr [[ARG]], align 2 38; CHECK-NEXT: [[STOREMERGE:%.*]] = trunc i16 [[STOREMERGE_IN]] to i8 39; CHECK-NEXT: store i8 [[STOREMERGE]], ptr @c, align 1 40; CHECK-NEXT: br label [[BB23:%.*]] 41; CHECK: bb23: 42; CHECK-NEXT: br label [[BB23]] 43; 44bb: 45 %i = load i64, ptr @d, align 8 46 %i1 = icmp eq i64 %i, 0 47 %i2 = load i64, ptr @a, align 8 48 %i3 = icmp ne i64 %i2, 0 49 br i1 %i1, label %bb13, label %bb4 50 51bb4: ; preds = %bb 52 %i5 = load i16, ptr %arg, align 2 53 %i6 = trunc i16 %i5 to i8 54 store i8 %i6, ptr @c, align 1 55 tail call void @llvm.assume(i1 %i3) 56 %i7 = load i16, ptr %arg, align 2 57 %i8 = trunc i16 %i7 to i8 58 store i8 %i8, ptr @c, align 1 59 %i9 = load i16, ptr %arg, align 2 60 %i10 = trunc i16 %i9 to i8 61 store i8 %i10, ptr @c, align 1 62 %i11 = load i16, ptr %arg, align 2 63 %i12 = trunc i16 %i11 to i8 64 store i8 %i12, ptr @c, align 1 65 br label %bb22 66 67bb13: ; preds = %bb 68 %i14 = load i16, ptr %arg, align 2 69 %i15 = trunc i16 %i14 to i8 70 store i8 %i15, ptr @c, align 1 71 %i16 = load i16, ptr %arg, align 2 72 %i17 = trunc i16 %i16 to i8 73 store i8 %i17, ptr @c, align 1 74 %i18 = load i16, ptr %arg, align 2 75 %i19 = trunc i16 %i18 to i8 76 store i8 %i19, ptr @c, align 1 77 %i20 = load i16, ptr %arg, align 2 78 %i21 = trunc i16 %i20 to i8 79 store i8 %i21, ptr @c, align 1 80 br label %bb22 81 82bb22: ; preds = %bb13, %bb4 83 br label %bb23 84 85bb23: ; preds = %bb23, %bb22 86 br label %bb23 87} 88 89; Function Attrs: nounwind willreturn 90declare void @llvm.assume(i1) #0 91 92attributes #0 = { nounwind willreturn } 93