1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes=instcombine -S | FileCheck %s 3 4target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" 5target triple = "i386-unknown-linux-gnu" 6 7define { i64, i64 } @mul_full_64(i64 %x, i64 %y) { 8; CHECK-LABEL: @mul_full_64( 9; CHECK-NEXT: [[XL:%.*]] = and i64 [[X:%.*]], 4294967295 10; CHECK-NEXT: [[XH:%.*]] = lshr i64 [[X]], 32 11; CHECK-NEXT: [[YL:%.*]] = and i64 [[Y:%.*]], 4294967295 12; CHECK-NEXT: [[YH:%.*]] = lshr i64 [[Y]], 32 13; CHECK-NEXT: [[T0:%.*]] = mul nuw i64 [[YL]], [[XL]] 14; CHECK-NEXT: [[T1:%.*]] = mul nuw i64 [[YL]], [[XH]] 15; CHECK-NEXT: [[T2:%.*]] = mul nuw i64 [[YH]], [[XL]] 16; CHECK-NEXT: [[T3:%.*]] = mul nuw i64 [[YH]], [[XH]] 17; CHECK-NEXT: [[T0L:%.*]] = and i64 [[T0]], 4294967295 18; CHECK-NEXT: [[T0H:%.*]] = lshr i64 [[T0]], 32 19; CHECK-NEXT: [[U0:%.*]] = add i64 [[T0H]], [[T1]] 20; CHECK-NEXT: [[U0L:%.*]] = and i64 [[U0]], 4294967295 21; CHECK-NEXT: [[U0H:%.*]] = lshr i64 [[U0]], 32 22; CHECK-NEXT: [[U1:%.*]] = add i64 [[U0L]], [[T2]] 23; CHECK-NEXT: [[U1LS:%.*]] = shl i64 [[U1]], 32 24; CHECK-NEXT: [[U1H:%.*]] = lshr i64 [[U1]], 32 25; CHECK-NEXT: [[U2:%.*]] = add i64 [[U0H]], [[T3]] 26; CHECK-NEXT: [[LO:%.*]] = or disjoint i64 [[U1LS]], [[T0L]] 27; CHECK-NEXT: [[HI:%.*]] = add i64 [[U2]], [[U1H]] 28; CHECK-NEXT: [[RES_LO:%.*]] = insertvalue { i64, i64 } undef, i64 [[LO]], 0 29; CHECK-NEXT: [[RES:%.*]] = insertvalue { i64, i64 } [[RES_LO]], i64 [[HI]], 1 30; CHECK-NEXT: ret { i64, i64 } [[RES]] 31; 32 %xl = and i64 %x, 4294967295 33 %xh = lshr i64 %x, 32 34 %yl = and i64 %y, 4294967295 35 %yh = lshr i64 %y, 32 36 37 %t0 = mul nuw i64 %yl, %xl 38 %t1 = mul nuw i64 %yl, %xh 39 %t2 = mul nuw i64 %yh, %xl 40 %t3 = mul nuw i64 %yh, %xh 41 42 %t0l = and i64 %t0, 4294967295 43 %t0h = lshr i64 %t0, 32 44 45 %u0 = add i64 %t0h, %t1 46 %u0l = and i64 %u0, 4294967295 47 %u0h = lshr i64 %u0, 32 48 49 %u1 = add i64 %u0l, %t2 50 %u1ls = shl i64 %u1, 32 51 %u1h = lshr i64 %u1, 32 52 53 %u2 = add i64 %u0h, %t3 54 55 %lo = or i64 %u1ls, %t0l 56 %hi = add i64 %u2, %u1h 57 58 %res_lo = insertvalue { i64, i64 } undef, i64 %lo, 0 59 %res = insertvalue { i64, i64 } %res_lo, i64 %hi, 1 60 ret { i64, i64 } %res 61} 62 63define { i32, i32 } @mul_full_32(i32 %x, i32 %y) { 64; CHECK-LABEL: @mul_full_32( 65; CHECK-NEXT: [[XL:%.*]] = and i32 [[X:%.*]], 65535 66; CHECK-NEXT: [[XH:%.*]] = lshr i32 [[X]], 16 67; CHECK-NEXT: [[YL:%.*]] = and i32 [[Y:%.*]], 65535 68; CHECK-NEXT: [[YH:%.*]] = lshr i32 [[Y]], 16 69; CHECK-NEXT: [[T0:%.*]] = mul nuw i32 [[YL]], [[XL]] 70; CHECK-NEXT: [[T1:%.*]] = mul nuw i32 [[YL]], [[XH]] 71; CHECK-NEXT: [[T2:%.*]] = mul nuw i32 [[YH]], [[XL]] 72; CHECK-NEXT: [[T3:%.*]] = mul nuw i32 [[YH]], [[XH]] 73; CHECK-NEXT: [[T0L:%.*]] = and i32 [[T0]], 65535 74; CHECK-NEXT: [[T0H:%.*]] = lshr i32 [[T0]], 16 75; CHECK-NEXT: [[U0:%.*]] = add i32 [[T0H]], [[T1]] 76; CHECK-NEXT: [[U0L:%.*]] = and i32 [[U0]], 65535 77; CHECK-NEXT: [[U0H:%.*]] = lshr i32 [[U0]], 16 78; CHECK-NEXT: [[U1:%.*]] = add i32 [[U0L]], [[T2]] 79; CHECK-NEXT: [[U1LS:%.*]] = shl i32 [[U1]], 16 80; CHECK-NEXT: [[U1H:%.*]] = lshr i32 [[U1]], 16 81; CHECK-NEXT: [[U2:%.*]] = add i32 [[U0H]], [[T3]] 82; CHECK-NEXT: [[LO:%.*]] = or disjoint i32 [[U1LS]], [[T0L]] 83; CHECK-NEXT: [[HI:%.*]] = add i32 [[U2]], [[U1H]] 84; CHECK-NEXT: [[RES_LO:%.*]] = insertvalue { i32, i32 } undef, i32 [[LO]], 0 85; CHECK-NEXT: [[RES:%.*]] = insertvalue { i32, i32 } [[RES_LO]], i32 [[HI]], 1 86; CHECK-NEXT: ret { i32, i32 } [[RES]] 87; 88 %xl = and i32 %x, 65535 89 %xh = lshr i32 %x, 16 90 %yl = and i32 %y, 65535 91 %yh = lshr i32 %y, 16 92 93 %t0 = mul nuw i32 %yl, %xl 94 %t1 = mul nuw i32 %yl, %xh 95 %t2 = mul nuw i32 %yh, %xl 96 %t3 = mul nuw i32 %yh, %xh 97 98 %t0l = and i32 %t0, 65535 99 %t0h = lshr i32 %t0, 16 100 101 %u0 = add i32 %t0h, %t1 102 %u0l = and i32 %u0, 65535 103 %u0h = lshr i32 %u0, 16 104 105 %u1 = add i32 %u0l, %t2 106 %u1ls = shl i32 %u1, 16 107 %u1h = lshr i32 %u1, 16 108 109 %u2 = add i32 %u0h, %t3 110 111 %lo = or i32 %u1ls, %t0l 112 %hi = add i32 %u2, %u1h 113 114 %res_lo = insertvalue { i32, i32 } undef, i32 %lo, 0 115 %res = insertvalue { i32, i32 } %res_lo, i32 %hi, 1 116 ret { i32, i32 } %res 117} 118