xref: /llvm-project/llvm/test/Transforms/InstCombine/minmax-demandbits.ll (revision 2caaec65c04ea7d0e9568b7895b7a46d6100cb75) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -S -passes=instcombine < %s | FileCheck %s
3
4
5define i32 @and_umax_less(i32 %A) {
6; CHECK-LABEL: @and_umax_less(
7; CHECK-NEXT:    [[X:%.*]] = and i32 [[A:%.*]], -32
8; CHECK-NEXT:    ret i32 [[X]]
9;
10  %l0 = icmp ugt i32 31, %A
11  %l1 = select i1 %l0, i32 31, i32 %A
12  %x = and i32 %l1, -32
13  ret i32 %x
14}
15
16define i32 @and_umax_muchless(i32 %A) {
17; CHECK-LABEL: @and_umax_muchless(
18; CHECK-NEXT:    [[X:%.*]] = and i32 [[A:%.*]], -32
19; CHECK-NEXT:    ret i32 [[X]]
20;
21  %l0 = icmp ugt i32 12, %A
22  %l1 = select i1 %l0, i32 12, i32 %A
23  %x = and i32 %l1, -32
24  ret i32 %x
25}
26
27define i32 @and_umax_more(i32 %A) {
28; CHECK-LABEL: @and_umax_more(
29; CHECK-NEXT:    [[L1:%.*]] = call i32 @llvm.umax.i32(i32 [[A:%.*]], i32 32)
30; CHECK-NEXT:    [[X:%.*]] = and i32 [[L1]], -32
31; CHECK-NEXT:    ret i32 [[X]]
32;
33  %l0 = icmp ugt i32 32, %A
34  %l1 = select i1 %l0, i32 32, i32 %A
35  %x = and i32 %l1, -32
36  ret i32 %x
37}
38
39define i32 @shr_umax(i32 %A) {
40; CHECK-LABEL: @shr_umax(
41; CHECK-NEXT:    [[X:%.*]] = lshr i32 [[A:%.*]], 4
42; CHECK-NEXT:    ret i32 [[X]]
43;
44  %l0 = icmp ugt i32 15, %A
45  %l1 = select i1 %l0, i32 15, i32 %A
46  %x = lshr i32 %l1, 4
47  ret i32 %x
48}
49
50; Various constants for C2 & umax(A, C1)
51
52define i8 @t_0_1(i8 %A) {
53; CHECK-LABEL: @t_0_1(
54; CHECK-NEXT:    [[X:%.*]] = and i8 [[A:%.*]], 1
55; CHECK-NEXT:    ret i8 [[X]]
56;
57  %l2 = icmp ugt i8 %A, 0
58  %l1 = select i1 %l2, i8 %A, i8 0
59  %x = and i8 %l1, 1
60  ret i8 %x
61}
62
63define i8 @t_0_10(i8 %A) {
64; CHECK-LABEL: @t_0_10(
65; CHECK-NEXT:    [[X:%.*]] = and i8 [[A:%.*]], 10
66; CHECK-NEXT:    ret i8 [[X]]
67;
68  %l2 = icmp ugt i8 %A, 0
69  %l1 = select i1 %l2, i8 %A, i8 0
70  %x = and i8 %l1, 10
71  ret i8 %x
72}
73
74define i8 @t_1_10(i8 %A) {
75; CHECK-LABEL: @t_1_10(
76; CHECK-NEXT:    [[X:%.*]] = and i8 [[A:%.*]], 10
77; CHECK-NEXT:    ret i8 [[X]]
78;
79  %l2 = icmp ugt i8 %A, 1
80  %l1 = select i1 %l2, i8 %A, i8 1
81  %x = and i8 %l1, 10
82  ret i8 %x
83}
84
85define i8 @t_2_4(i8 %A) {
86; CHECK-LABEL: @t_2_4(
87; CHECK-NEXT:    [[X:%.*]] = and i8 [[A:%.*]], 4
88; CHECK-NEXT:    ret i8 [[X]]
89;
90  %l2 = icmp ugt i8 %A, 2
91  %l1 = select i1 %l2, i8 %A, i8 2
92  %x = and i8 %l1, 4
93  ret i8 %x
94}
95
96define i8 @t_2_192(i8 %A) {
97; CHECK-LABEL: @t_2_192(
98; CHECK-NEXT:    [[X:%.*]] = and i8 [[A:%.*]], -64
99; CHECK-NEXT:    ret i8 [[X]]
100;
101  %l2 = icmp ugt i8 %A, 2
102  %l1 = select i1 %l2, i8 %A, i8 2
103  %x = and i8 %l1, -64
104  ret i8 %x
105}
106
107define i8 @t_2_63_or(i8 %A) {
108; CHECK-LABEL: @t_2_63_or(
109; CHECK-NEXT:    [[X:%.*]] = or i8 [[A:%.*]], 63
110; CHECK-NEXT:    ret i8 [[X]]
111;
112  %l2 = icmp ugt i8 %A, 2
113  %l1 = select i1 %l2, i8 %A, i8 2
114  %x = or i8 %l1, 63
115  ret i8 %x
116}
117
118define i8 @f_1_1(i8 %A) {
119; CHECK-LABEL: @f_1_1(
120; CHECK-NEXT:    [[L1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 1)
121; CHECK-NEXT:    [[X:%.*]] = and i8 [[L1]], 1
122; CHECK-NEXT:    ret i8 [[X]]
123;
124  %l2 = icmp ugt i8 %A, 1
125  %l1 = select i1 %l2, i8 %A, i8 1
126  %x = and i8 %l1, 1
127  ret i8 %x
128}
129
130define i8 @f_32_32(i8 %A) {
131; CHECK-LABEL: @f_32_32(
132; CHECK-NEXT:    [[L1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 32)
133; CHECK-NEXT:    [[X:%.*]] = and i8 [[L1]], -32
134; CHECK-NEXT:    ret i8 [[X]]
135;
136  %l2 = icmp ugt i8 %A, 32
137  %l1 = select i1 %l2, i8 %A, i8 32
138  %x = and i8 %l1, -32
139  ret i8 %x
140}
141
142define i8 @f_191_192(i8 %A) {
143; CHECK-LABEL: @f_191_192(
144; CHECK-NEXT:    [[L1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 -65)
145; CHECK-NEXT:    [[X:%.*]] = and i8 [[L1]], -64
146; CHECK-NEXT:    ret i8 [[X]]
147;
148  %l2 = icmp ugt i8 %A, 191
149  %l1 = select i1 %l2, i8 %A, i8 191
150  %x = and i8 %l1, 192
151  ret i8 %x
152}
153
154define i8 @f_10_1(i8 %A) {
155; CHECK-LABEL: @f_10_1(
156; CHECK-NEXT:    [[L1:%.*]] = call i8 @llvm.umax.i8(i8 [[A:%.*]], i8 10)
157; CHECK-NEXT:    [[X:%.*]] = and i8 [[L1]], 1
158; CHECK-NEXT:    ret i8 [[X]]
159;
160  %l2 = icmp ugt i8 %A, 10
161  %l1 = select i1 %l2, i8 %A, i8 10
162  %x = and i8 %l1, 1
163  ret i8 %x
164}
165
166define i32 @and_umin(i32 %A) {
167; CHECK-LABEL: @and_umin(
168; CHECK-NEXT:    ret i32 0
169;
170  %l0 = icmp ult i32 15, %A
171  %l1 = select i1 %l0, i32 15, i32 %A
172  %x = and i32 %l1, -32
173  ret i32 %x
174}
175
176define i32 @or_umin(i32 %A) {
177; CHECK-LABEL: @or_umin(
178; CHECK-NEXT:    ret i32 31
179;
180  %l0 = icmp ult i32 15, %A
181  %l1 = select i1 %l0, i32 15, i32 %A
182  %x = or i32 %l1, 31
183  ret i32 %x
184}
185
186define i8 @or_min_31_30(i8 %A) {
187; CHECK-LABEL: @or_min_31_30(
188; CHECK-NEXT:    [[R:%.*]] = or i8 [[A:%.*]], 31
189; CHECK-NEXT:    ret i8 [[R]]
190;
191  %cmp = icmp ult i8 %A, -30
192  %min = select i1 %cmp, i8 %A, i8 -30
193  %r = or i8 %min, 31
194  ret i8 %r
195}
196
197define i8 @and_min_7_7(i8 %A) {
198; CHECK-LABEL: @and_min_7_7(
199; CHECK-NEXT:    [[R:%.*]] = and i8 [[A:%.*]], -8
200; CHECK-NEXT:    ret i8 [[R]]
201;
202  %l2 = icmp ult i8 %A, -7
203  %min = select i1 %l2, i8 %A, i8 -7
204  %r = and i8 %min, -8
205  ret i8 %r
206}
207
208define i8 @and_min_7_8(i8 %A) {
209; CHECK-LABEL: @and_min_7_8(
210; CHECK-NEXT:    [[R:%.*]] = and i8 [[A:%.*]], -8
211; CHECK-NEXT:    ret i8 [[R]]
212;
213  %l2 = icmp ult i8 %A, -8
214  %min = select i1 %l2, i8 %A, i8 -8
215  %r = and i8 %min, -8
216  ret i8 %r
217}
218
219define i8 @and_min_7_9(i8 %A) {
220; CHECK-LABEL: @and_min_7_9(
221; CHECK-NEXT:    [[MIN:%.*]] = call i8 @llvm.umin.i8(i8 [[A:%.*]], i8 -9)
222; CHECK-NEXT:    [[R:%.*]] = and i8 [[MIN]], -8
223; CHECK-NEXT:    ret i8 [[R]]
224;
225  %l2 = icmp ult i8 %A, -9
226  %min = select i1 %l2, i8 %A, i8 -9
227  %r = and i8 %min, -8
228  ret i8 %r
229}
230
231