xref: /llvm-project/llvm/test/Transforms/InstCombine/known-fpclass-reduce-signbit.ll (revision 9eeae4421198b99eab3ae9a4ff678fda26bbda2a) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
2; RUN: opt < %s -S -passes=instcombine | FileCheck %s
3
4define i1 @vector_reduce_maximum_signbit(<4 x double> nofpclass(nan nzero) %x) {
5; CHECK-LABEL: define i1 @vector_reduce_maximum_signbit
6; CHECK-SAME: (<4 x double> nofpclass(nan nzero) [[X:%.*]]) {
7; CHECK-NEXT:    ret i1 true
8;
9  %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)
10  %op = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> %x.abs)
11  %cmp = fcmp oge double %op, 0.0
12  ret i1 %cmp
13}
14
15define i1 @vector_reduce_maximum_signbit_fail_maybe_nan(<4 x double> nofpclass(nzero) %x) {
16; CHECK-LABEL: define i1 @vector_reduce_maximum_signbit_fail_maybe_nan
17; CHECK-SAME: (<4 x double> nofpclass(nzero) [[X:%.*]]) {
18; CHECK-NEXT:    [[X_ABS:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[X]])
19; CHECK-NEXT:    [[OP:%.*]] = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> [[X_ABS]])
20; CHECK-NEXT:    [[CMP:%.*]] = fcmp oge double [[OP]], 0.000000e+00
21; CHECK-NEXT:    ret i1 [[CMP]]
22;
23  %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)
24  %op = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> %x.abs)
25  %cmp = fcmp oge double %op, 0.0
26  ret i1 %cmp
27}
28
29
30define i1 @vector_reduce_minimum_signbit(<4 x double> nofpclass(nan nzero) %x) {
31; CHECK-LABEL: define i1 @vector_reduce_minimum_signbit
32; CHECK-SAME: (<4 x double> nofpclass(nan nzero) [[X:%.*]]) {
33; CHECK-NEXT:    ret i1 true
34;
35  %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)
36  %op = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> %x.abs)
37  %cmp = fcmp oge double %op, 0.0
38  ret i1 %cmp
39}
40
41define i1 @vector_reduce_minimum_signbit_fail_maybe_nan(<4 x double> nofpclass(nzero) %x) {
42; CHECK-LABEL: define i1 @vector_reduce_minimum_signbit_fail_maybe_nan
43; CHECK-SAME: (<4 x double> nofpclass(nzero) [[X:%.*]]) {
44; CHECK-NEXT:    [[X_ABS:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[X]])
45; CHECK-NEXT:    [[OP:%.*]] = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> [[X_ABS]])
46; CHECK-NEXT:    [[CMP:%.*]] = fcmp oge double [[OP]], 0.000000e+00
47; CHECK-NEXT:    ret i1 [[CMP]]
48;
49  %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)
50  %op = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> %x.abs)
51  %cmp = fcmp oge double %op, 0.0
52  ret i1 %cmp
53}
54
55define i1 @vector_reduce_max_signbit(<4 x double> nofpclass(nan nzero) %x) {
56; CHECK-LABEL: define i1 @vector_reduce_max_signbit
57; CHECK-SAME: (<4 x double> nofpclass(nan nzero) [[X:%.*]]) {
58; CHECK-NEXT:    ret i1 true
59;
60  %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)
61  %op = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x.abs)
62  %cmp = fcmp oge double %op, 0.0
63  ret i1 %cmp
64}
65
66define i1 @vector_reduce_max_signbit_fail_maybe_nan(<4 x double> nofpclass(nzero) %x) {
67; CHECK-LABEL: define i1 @vector_reduce_max_signbit_fail_maybe_nan
68; CHECK-SAME: (<4 x double> nofpclass(nzero) [[X:%.*]]) {
69; CHECK-NEXT:    [[X_ABS:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[X]])
70; CHECK-NEXT:    [[OP:%.*]] = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> [[X_ABS]])
71; CHECK-NEXT:    [[CMP:%.*]] = fcmp oge double [[OP]], 0.000000e+00
72; CHECK-NEXT:    ret i1 [[CMP]]
73;
74  %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)
75  %op = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %x.abs)
76  %cmp = fcmp oge double %op, 0.0
77  ret i1 %cmp
78}
79
80
81define i1 @vector_reduce_min_signbit(<4 x double> nofpclass(nan nzero) %x) {
82; CHECK-LABEL: define i1 @vector_reduce_min_signbit
83; CHECK-SAME: (<4 x double> nofpclass(nan nzero) [[X:%.*]]) {
84; CHECK-NEXT:    ret i1 true
85;
86  %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)
87  %op = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x.abs)
88  %cmp = fcmp oge double %op, 0.0
89  ret i1 %cmp
90}
91
92define i1 @vector_reduce_min_signbit_fail_maybe_nan(<4 x double> nofpclass(nzero) %x) {
93; CHECK-LABEL: define i1 @vector_reduce_min_signbit_fail_maybe_nan
94; CHECK-SAME: (<4 x double> nofpclass(nzero) [[X:%.*]]) {
95; CHECK-NEXT:    [[X_ABS:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[X]])
96; CHECK-NEXT:    [[OP:%.*]] = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> [[X_ABS]])
97; CHECK-NEXT:    [[CMP:%.*]] = fcmp oge double [[OP]], 0.000000e+00
98; CHECK-NEXT:    ret i1 [[CMP]]
99;
100  %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)
101  %op = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x.abs)
102  %cmp = fcmp oge double %op, 0.0
103  ret i1 %cmp
104}
105
106
107
108define i1 @vector_reduce_min_signbit_nnan_from_fmf(<4 x double> nofpclass(nzero) %x) {
109; CHECK-LABEL: define i1 @vector_reduce_min_signbit_nnan_from_fmf
110; CHECK-SAME: (<4 x double> nofpclass(nzero) [[X:%.*]]) {
111; CHECK-NEXT:    ret i1 true
112;
113  %x.abs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)
114  %op = call nnan double @llvm.vector.reduce.fmin.v4f64(<4 x double> %x.abs)
115  %cmp = fcmp oge double %op, 0.0
116  ret i1 %cmp
117}
118
119
120