xref: /llvm-project/llvm/test/Transforms/InstCombine/div-by-0-guard-before-umul_ov.ll (revision 060de415af335fdd82910f409e2be3b8457eaa43) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt %s -passes=instcombine -S | FileCheck %s
3
4declare { i4, i1 } @llvm.umul.with.overflow.i4(i4, i4) #1
5
6define i1 @t0_umul(i4 %size, i4 %nmemb) {
7; CHECK-LABEL: @t0_umul(
8; CHECK-NEXT:    [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE:%.*]], i4 [[NMEMB:%.*]])
9; CHECK-NEXT:    [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
10; CHECK-NEXT:    ret i1 [[UMUL_OV]]
11;
12  %cmp = icmp ne i4 %size, 0
13  %umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
14  %umul.ov = extractvalue { i4, i1 } %umul, 1
15  %and = select i1 %umul.ov, i1 %cmp, i1 false
16  ret i1 %and
17}
18
19define i1 @t1_commutative(i4 %size, i4 %nmemb) {
20; CHECK-LABEL: @t1_commutative(
21; CHECK-NEXT:    [[NMEMB_FR:%.*]] = freeze i4 [[NMEMB:%.*]]
22; CHECK-NEXT:    [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE:%.*]], i4 [[NMEMB_FR]])
23; CHECK-NEXT:    [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
24; CHECK-NEXT:    ret i1 [[UMUL_OV]]
25;
26  %cmp = icmp ne i4 %size, 0
27  %umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
28  %umul.ov = extractvalue { i4, i1 } %umul, 1
29  %and = select i1 %cmp, i1 %umul.ov, i1 false ; swapped
30  ret i1 %and
31}
32
33define i1 @n2_wrong_size(i4 %size0, i4 %size1, i4 %nmemb) {
34; CHECK-LABEL: @n2_wrong_size(
35; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i4 [[SIZE1:%.*]], 0
36; CHECK-NEXT:    [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE0:%.*]], i4 [[NMEMB:%.*]])
37; CHECK-NEXT:    [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
38; CHECK-NEXT:    [[AND:%.*]] = select i1 [[UMUL_OV]], i1 [[CMP]], i1 false
39; CHECK-NEXT:    ret i1 [[AND]]
40;
41  %cmp = icmp ne i4 %size1, 0 ; not %size0
42  %umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size0, i4 %nmemb)
43  %umul.ov = extractvalue { i4, i1 } %umul, 1
44  %and = select i1 %umul.ov, i1 %cmp, i1 false
45  ret i1 %and
46}
47
48define i1 @n3_wrong_pred(i4 %size, i4 %nmemb) {
49; CHECK-LABEL: @n3_wrong_pred(
50; CHECK-NEXT:    ret i1 false
51;
52  %cmp = icmp eq i4 %size, 0 ; not 'ne'
53  %umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
54  %umul.ov = extractvalue { i4, i1 } %umul, 1
55  %and = select i1 %umul.ov, i1 %cmp, i1 false
56  ret i1 %and
57}
58
59define i1 @n4_not_and(i4 %size, i4 %nmemb) {
60; CHECK-LABEL: @n4_not_and(
61; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 0
62; CHECK-NEXT:    ret i1 [[CMP]]
63;
64  %cmp = icmp ne i4 %size, 0
65  %umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
66  %umul.ov = extractvalue { i4, i1 } %umul, 1
67  %and = select i1 %umul.ov, i1 true, i1 %cmp ; not 'and'
68  ret i1 %and
69}
70
71define i1 @n5_not_zero(i4 %size, i4 %nmemb) {
72; CHECK-LABEL: @n5_not_zero(
73; CHECK-NEXT:    [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 1
74; CHECK-NEXT:    [[UMUL:%.*]] = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
75; CHECK-NEXT:    [[UMUL_OV:%.*]] = extractvalue { i4, i1 } [[UMUL]], 1
76; CHECK-NEXT:    [[AND:%.*]] = and i1 [[UMUL_OV]], [[CMP]]
77; CHECK-NEXT:    ret i1 [[AND]]
78;
79  %cmp = icmp ne i4 %size, 1 ; should be '0'
80  %umul = tail call { i4, i1 } @llvm.umul.with.overflow.i4(i4 %size, i4 %nmemb)
81  %umul.ov = extractvalue { i4, i1 } %umul, 1
82  %and = select i1 %umul.ov, i1 %cmp, i1 false
83  ret i1 %and
84}
85