xref: /llvm-project/llvm/test/Transforms/InstCombine/ashr-demand.ll (revision 38fffa630ee80163dc65e759392ad29798905679)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -passes=instcombine -S < %s | FileCheck %s
3
4; If we only want bits that already match the signbit then we don't need to shift.
5
6define i32 @srem2_ashr_mask(i32 %a0) {
7; CHECK-LABEL: @srem2_ashr_mask(
8; CHECK-NEXT:    [[SREM:%.*]] = srem i32 [[A0:%.*]], 2
9; CHECK-NEXT:    [[MASK:%.*]] = and i32 [[SREM]], 2
10; CHECK-NEXT:    ret i32 [[MASK]]
11;
12  %srem = srem i32 %a0, 2 ; result = (1,0,-1) num signbits = 31
13  %ashr = ashr i32 %srem, 31
14  %mask = and i32 %ashr, 2
15  ret i32 %mask
16}
17
18; Negative test - mask demands non-signbit from shift source
19define i32 @srem8_ashr_mask(i32 %a0) {
20; CHECK-LABEL: @srem8_ashr_mask(
21; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A0:%.*]], -2147483641
22; CHECK-NEXT:    [[ISNEG:%.*]] = icmp ugt i32 [[TMP1]], -2147483648
23; CHECK-NEXT:    [[MASK:%.*]] = select i1 [[ISNEG]], i32 2, i32 0
24; CHECK-NEXT:    ret i32 [[MASK]]
25;
26  %srem = srem i32 %a0, 8
27  %ashr = ashr i32 %srem, 31
28  %mask = and i32 %ashr, 2
29  ret i32 %mask
30}
31
32define <2 x i32> @srem2_ashr_mask_vector(<2 x i32> %a0) {
33; CHECK-LABEL: @srem2_ashr_mask_vector(
34; CHECK-NEXT:    [[SREM:%.*]] = srem <2 x i32> [[A0:%.*]], splat (i32 2)
35; CHECK-NEXT:    [[MASK:%.*]] = and <2 x i32> [[SREM]], splat (i32 2)
36; CHECK-NEXT:    ret <2 x i32> [[MASK]]
37;
38  %srem = srem <2 x i32> %a0, <i32 2, i32 2>
39  %ashr = ashr <2 x i32> %srem, <i32 31, i32 31>
40  %mask = and <2 x i32> %ashr, <i32 2, i32 2>
41  ret <2 x i32> %mask
42}
43
44define <2 x i32> @srem2_ashr_mask_vector_nonconstant(<2 x i32> %a0, <2 x i32> %a1) {
45; CHECK-LABEL: @srem2_ashr_mask_vector_nonconstant(
46; CHECK-NEXT:    [[SREM:%.*]] = srem <2 x i32> [[A0:%.*]], splat (i32 2)
47; CHECK-NEXT:    [[MASK:%.*]] = and <2 x i32> [[SREM]], splat (i32 2)
48; CHECK-NEXT:    ret <2 x i32> [[MASK]]
49;
50  %srem = srem <2 x i32> %a0, <i32 2, i32 2>
51  %ashr = ashr <2 x i32> %srem, %a1
52  %mask = and <2 x i32> %ashr, <i32 2, i32 2>
53  ret <2 x i32> %mask
54}
55
56
57; If it does not matter if we do ashr or lshr, then we canonicalize to lshr.
58
59define i16 @ashr_can_be_lshr(i32 %a) {
60; CHECK-LABEL: @ashr_can_be_lshr(
61; CHECK-NEXT:    [[ASHR:%.*]] = lshr exact i32 [[A:%.*]], 16
62; CHECK-NEXT:    [[TRUNC:%.*]] = trunc nuw i32 [[ASHR]] to i16
63; CHECK-NEXT:    ret i16 [[TRUNC]]
64;
65  %ashr = ashr exact i32 %a, 16
66  %trunc = trunc nsw i32 %ashr to i16
67  ret i16 %trunc
68}
69
70; Historically SimplifyDemandedUseBits skipped replacing ashr with lshr here
71; due to known sign bits analysis indicating that %ashr had more than 33 sign
72; bits. It does however seem weird not to always canonicalize to lshr when
73; possible, and in this case rewriting into lshr would trigger further
74; optimizations.
75define i32 @ashr_can_be_lshr_2(i32 %a) {
76; CHECK-LABEL: @ashr_can_be_lshr_2(
77; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[A:%.*]], 2
78; CHECK-NEXT:    [[TMP2:%.*]] = or i32 [[TMP1]], -67108864
79; CHECK-NEXT:    ret i32 [[TMP2]]
80;
81  %ext = zext i32 %a to i64
82  %or = or i64 %ext, 4278190080
83  %shl = shl i64 %or, 34
84  %ashr = ashr exact i64 %shl, 32
85  %trunc = trunc nsw i64 %ashr to i32
86  ret i32 %trunc
87}
88