xref: /llvm-project/llvm/test/Transforms/InstCombine/addnegneg.ll (revision 3f6a8e9b18154accc78e620b843b3721c23703b1)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2; RUN: opt < %s -passes=instcombine -S | FileCheck %s
3; PR2047
4
5define i32 @l(i32 %a, i32 %b, i32 %c, i32 %d) {
6; CHECK-LABEL: define i32 @l(
7; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]], i32 [[D:%.*]]) {
8; CHECK-NEXT:  entry:
9; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[C]], [[B]]
10; CHECK-NEXT:    [[SUB6:%.*]] = sub i32 [[D]], [[TMP0]]
11; CHECK-NEXT:    ret i32 [[SUB6]]
12;
13entry:
14  %b.neg = sub i32 0, %b		; <i32> [#uses=1]
15  %c.neg = sub i32 0, %c		; <i32> [#uses=1]
16  %sub4 = add i32 %c.neg, %b.neg		; <i32> [#uses=1]
17  %sub6 = add i32 %sub4, %d		; <i32> [#uses=1]
18  ret i32 %sub6
19}
20