xref: /llvm-project/llvm/test/Transforms/InstCombine/AArch64/neon-min-max-intrinsics.ll (revision 17a73992dd8ba831e47b29b41d5c20292992a810) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -passes=instcombine -mtriple=arm64-apple-ios -S %s | FileCheck %s
3
4declare <4 x half> @llvm.aarch64.neon.fmaxnm.v4f16(<4 x half>, <4 x half>)
5declare <4 x float> @llvm.aarch64.neon.fmaxnm.v4f32(<4 x float>, <4 x float>)
6declare <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double>, <2 x double>)
7
8define <4 x half> @fmaxnm_v4f16_same_args(<4 x half> %a) {
9; CHECK-LABEL: @fmaxnm_v4f16_same_args(
10; CHECK-NEXT:    ret <4 x half> [[A:%.*]]
11;
12  %r = call <4 x half> @llvm.aarch64.neon.fmaxnm.v4f16(<4 x half> %a, <4 x half> %a)
13  ret <4 x half> %r
14}
15
16define <4 x half> @fmaxnm_v4f16_different_args(<4 x half> %a, <4 x half> %b) {
17; CHECK-LABEL: @fmaxnm_v4f16_different_args(
18; CHECK-NEXT:    [[R:%.*]] = call <4 x half> @llvm.aarch64.neon.fmaxnm.v4f16(<4 x half> [[A:%.*]], <4 x half> [[B:%.*]])
19; CHECK-NEXT:    ret <4 x half> [[R]]
20;
21  %r = call <4 x half> @llvm.aarch64.neon.fmaxnm.v4f16(<4 x half> %a, <4 x half> %b)
22  ret <4 x half> %r
23}
24
25define <4 x float> @fmaxnm_v4f32_same_args(<4 x float> %a) {
26; CHECK-LABEL: @fmaxnm_v4f32_same_args(
27; CHECK-NEXT:    ret <4 x float> [[A:%.*]]
28;
29  %r = call <4 x float> @llvm.aarch64.neon.fmaxnm.v4f32(<4 x float> %a, <4 x float> %a)
30  ret <4 x float> %r
31}
32
33define <4 x float> @fmaxnm_v4f32_different_args(<4 x float> %a, <4 x float> %b) {
34; CHECK-LABEL: @fmaxnm_v4f32_different_args(
35; CHECK-NEXT:    [[R:%.*]] = call <4 x float> @llvm.aarch64.neon.fmaxnm.v4f32(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]])
36; CHECK-NEXT:    ret <4 x float> [[R]]
37;
38  %r = call <4 x float> @llvm.aarch64.neon.fmaxnm.v4f32(<4 x float> %a, <4 x float> %b)
39  ret <4 x float> %r
40}
41
42define <2 x double> @fmaxnm_v2f64_same_args(<2 x double> %a) {
43; CHECK-LABEL: @fmaxnm_v2f64_same_args(
44; CHECK-NEXT:    ret <2 x double> [[A:%.*]]
45;
46  %r = call <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double> %a, <2 x double> %a)
47  ret <2 x double> %r
48}
49
50define <2 x double> @fmaxnm_v2f64_different_args(<2 x double> %a, <2 x double> %b) {
51; CHECK-LABEL: @fmaxnm_v2f64_different_args(
52; CHECK-NEXT:    [[R:%.*]] = call <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]])
53; CHECK-NEXT:    ret <2 x double> [[R]]
54;
55  %r = call <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double> %a, <2 x double> %b)
56  ret <2 x double> %r
57}
58
59declare <4 x half> @llvm.aarch64.neon.fminnm.v4f16(<4 x half>, <4 x half>)
60declare <4 x float> @llvm.aarch64.neon.fminnm.v4f32(<4 x float>, <4 x float>)
61declare <2 x double> @llvm.aarch64.neon.fminnm.v2f64(<2 x double>, <2 x double>)
62
63define <4 x half> @fminnm_v4f16_same_args(<4 x half> %a) {
64; CHECK-LABEL: @fminnm_v4f16_same_args(
65; CHECK-NEXT:    ret <4 x half> [[A:%.*]]
66;
67  %r = call <4 x half> @llvm.aarch64.neon.fminnm.v4f16(<4 x half> %a, <4 x half> %a)
68  ret <4 x half> %r
69}
70
71define <4 x half> @fminnm_v4f16_different_args(<4 x half> %a, <4 x half> %b) {
72; CHECK-LABEL: @fminnm_v4f16_different_args(
73; CHECK-NEXT:    [[R:%.*]] = call <4 x half> @llvm.aarch64.neon.fminnm.v4f16(<4 x half> [[A:%.*]], <4 x half> [[B:%.*]])
74; CHECK-NEXT:    ret <4 x half> [[R]]
75;
76  %r = call <4 x half> @llvm.aarch64.neon.fminnm.v4f16(<4 x half> %a, <4 x half> %b)
77  ret <4 x half> %r
78}
79
80define <4 x float> @fminnm_v4f32_same_args(<4 x float> %a) {
81; CHECK-LABEL: @fminnm_v4f32_same_args(
82; CHECK-NEXT:    ret <4 x float> [[A:%.*]]
83;
84  %r = call <4 x float> @llvm.aarch64.neon.fminnm.v4f32(<4 x float> %a, <4 x float> %a)
85  ret <4 x float> %r
86}
87
88define <4 x float> @fminnm_v4f32_different_args(<4 x float> %a, <4 x float> %b) {
89; CHECK-LABEL: @fminnm_v4f32_different_args(
90; CHECK-NEXT:    [[R:%.*]] = call <4 x float> @llvm.aarch64.neon.fminnm.v4f32(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]])
91; CHECK-NEXT:    ret <4 x float> [[R]]
92;
93  %r = call <4 x float> @llvm.aarch64.neon.fminnm.v4f32(<4 x float> %a, <4 x float> %b)
94  ret <4 x float> %r
95}
96
97define <2 x double> @fminnm_v2f64_same_args(<2 x double> %a) {
98; CHECK-LABEL: @fminnm_v2f64_same_args(
99; CHECK-NEXT:    ret <2 x double> [[A:%.*]]
100;
101  %r = call <2 x double> @llvm.aarch64.neon.fminnm.v2f64(<2 x double> %a, <2 x double> %a)
102  ret <2 x double> %r
103}
104
105define <2 x double> @fminnm_v2f64_different_args(<2 x double> %a, <2 x double> %b) {
106; CHECK-LABEL: @fminnm_v2f64_different_args(
107; CHECK-NEXT:    [[R:%.*]] = call <2 x double> @llvm.aarch64.neon.fminnm.v2f64(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]])
108; CHECK-NEXT:    ret <2 x double> [[R]]
109;
110  %r = call <2 x double> @llvm.aarch64.neon.fminnm.v2f64(<2 x double> %a, <2 x double> %b)
111  ret <2 x double> %r
112}
113