xref: /llvm-project/llvm/test/Transforms/InstCombine/2008-02-28-OrFCmpCrash.ll (revision acdc419c897f8a9414c7a00c8908ac32312afee2)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -passes=instcombine -S | FileCheck %s
3
4; rdar://5771353
5
6define float @test(float %x, x86_fp80 %y) nounwind readonly  {
7; CHECK-LABEL: @test(
8; CHECK-NEXT:  entry:
9; CHECK-NEXT:    [[TMP67:%.*]] = fcmp uno x86_fp80 [[Y:%.*]], 0xK00000000000000000000
10; CHECK-NEXT:    [[TMP71:%.*]] = fcmp uno float [[X:%.*]], 0.000000e+00
11; CHECK-NEXT:    [[BOTHCOND:%.*]] = or i1 [[TMP67]], [[TMP71]]
12; CHECK-NEXT:    br i1 [[BOTHCOND]], label [[BB74:%.*]], label [[BB80:%.*]]
13; CHECK:       bb74:
14; CHECK-NEXT:    ret float 0.000000e+00
15; CHECK:       bb80:
16; CHECK-NEXT:    ret float 0.000000e+00
17;
18entry:
19  %tmp67 = fcmp uno x86_fp80 %y, 0xK00000000000000000000		; <i1> [#uses=1]
20  %tmp71 = fcmp uno float %x, 0.000000e+00		; <i1> [#uses=1]
21  %bothcond = or i1 %tmp67, %tmp71		; <i1> [#uses=1]
22  br i1 %bothcond, label %bb74, label %bb80
23
24bb74:		; preds = %entry
25  ret float 0.000000e+00
26
27bb80:		; preds = %entry
28  ret float 0.000000e+00
29}
30
31define float @test_logical(float %x, x86_fp80 %y) nounwind readonly  {
32; CHECK-LABEL: @test_logical(
33; CHECK-NEXT:  entry:
34; CHECK-NEXT:    [[TMP67:%.*]] = fcmp uno x86_fp80 [[Y:%.*]], 0xK00000000000000000000
35; CHECK-NEXT:    [[TMP71:%.*]] = fcmp uno float [[X:%.*]], 0.000000e+00
36; CHECK-NEXT:    [[BOTHCOND:%.*]] = select i1 [[TMP67]], i1 true, i1 [[TMP71]]
37; CHECK-NEXT:    br i1 [[BOTHCOND]], label [[BB74:%.*]], label [[BB80:%.*]]
38; CHECK:       bb74:
39; CHECK-NEXT:    ret float 0.000000e+00
40; CHECK:       bb80:
41; CHECK-NEXT:    ret float 0.000000e+00
42;
43entry:
44  %tmp67 = fcmp uno x86_fp80 %y, 0xK00000000000000000000		; <i1> [#uses=1]
45  %tmp71 = fcmp uno float %x, 0.000000e+00		; <i1> [#uses=1]
46  %bothcond = select i1 %tmp67, i1 true, i1 %tmp71		; <i1> [#uses=1]
47  br i1 %bothcond, label %bb74, label %bb80
48
49bb74:		; preds = %entry
50  ret float 0.000000e+00
51
52bb80:		; preds = %entry
53  ret float 0.000000e+00
54}
55