1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs 2; RUN: opt -S -passes=verify,iroutliner -ir-outlining-no-cost < %s | FileCheck %s 3 4; Here we have multiple exits, but the different sources, same outputs are 5; needed, this checks that they are compressed, and moved into the appropriate 6; output blocks. 7 8define void @outline_outputs1() #0 { 9entry: 10 %output = alloca i32, align 4 11 %result = alloca i32, align 4 12 %output2 = alloca i32, align 4 13 %result2 = alloca i32, align 4 14 %a = alloca i32, align 4 15 %b = alloca i32, align 4 16 br label %block_2 17block_1: 18 %a2 = alloca i32, align 4 19 %b2 = alloca i32, align 4 20 br label %block_2 21block_2: 22 %a2val = load i32, ptr %a 23 %b2val = load i32, ptr %b 24 %add2 = add i32 2, %a2val 25 %mul2 = mul i32 2, %b2val 26 br label %block_5 27block_3: 28 %aval = load i32, ptr %a 29 %bval = load i32, ptr %b 30 %add = add i32 2, %aval 31 %mul = mul i32 2, %bval 32 br label %block_4 33block_4: 34 store i32 %add, ptr %output, align 4 35 store i32 %mul, ptr %result, align 4 36 br label %block_6 37block_5: 38 store i32 %add2, ptr %output, align 4 39 store i32 %mul2, ptr %result, align 4 40 br label %block_7 41block_6: 42 %div = udiv i32 %aval, %bval 43 ret void 44block_7: 45 %sub = sub i32 %a2val, %b2val 46 ret void 47} 48 49define void @outline_outputs2() #0 { 50entry: 51 %output = alloca i32, align 4 52 %result = alloca i32, align 4 53 %output2 = alloca i32, align 4 54 %result2 = alloca i32, align 4 55 %a = alloca i32, align 4 56 %b = alloca i32, align 4 57 br label %block_2 58block_1: 59 %a2 = alloca i32, align 4 60 %b2 = alloca i32, align 4 61 br label %block_2 62block_2: 63 %a2val = load i32, ptr %a 64 %b2val = load i32, ptr %b 65 %add2 = add i32 2, %a2val 66 %mul2 = mul i32 2, %b2val 67 br label %block_5 68block_3: 69 %aval = load i32, ptr %a 70 %bval = load i32, ptr %b 71 %add = add i32 2, %aval 72 %mul = mul i32 2, %bval 73 br label %block_4 74block_4: 75 store i32 %add, ptr %output, align 4 76 store i32 %mul, ptr %result, align 4 77 br label %block_7 78block_5: 79 store i32 %add2, ptr %output, align 4 80 store i32 %mul2, ptr %result, align 4 81 br label %block_6 82block_6: 83 %diff = sub i32 %a2val, %b2val 84 ret void 85block_7: 86 %quot = udiv i32 %aval, %bval 87 ret void 88} 89; CHECK-LABEL: @outline_outputs1( 90; CHECK-NEXT: entry: 91; CHECK-NEXT: [[BVAL_LOC:%.*]] = alloca i32, align 4 92; CHECK-NEXT: [[AVAL_LOC:%.*]] = alloca i32, align 4 93; CHECK-NEXT: [[B2VAL_LOC:%.*]] = alloca i32, align 4 94; CHECK-NEXT: [[A2VAL_LOC:%.*]] = alloca i32, align 4 95; CHECK-NEXT: [[OUTPUT:%.*]] = alloca i32, align 4 96; CHECK-NEXT: [[RESULT:%.*]] = alloca i32, align 4 97; CHECK-NEXT: [[OUTPUT2:%.*]] = alloca i32, align 4 98; CHECK-NEXT: [[RESULT2:%.*]] = alloca i32, align 4 99; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 100; CHECK-NEXT: [[B:%.*]] = alloca i32, align 4 101; CHECK-NEXT: br label [[BLOCK_2:%.*]] 102; CHECK: block_1: 103; CHECK-NEXT: [[A2:%.*]] = alloca i32, align 4 104; CHECK-NEXT: [[B2:%.*]] = alloca i32, align 4 105; CHECK-NEXT: br label [[BLOCK_2]] 106; CHECK: block_2: 107; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[A2VAL_LOC]]) 108; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[B2VAL_LOC]]) 109; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[AVAL_LOC]]) 110; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[BVAL_LOC]]) 111; CHECK-NEXT: [[TARGETBLOCK:%.*]] = call i1 @outlined_ir_func_0(ptr [[A]], ptr [[B]], ptr [[OUTPUT]], ptr [[RESULT]], ptr [[A2VAL_LOC]], ptr [[B2VAL_LOC]], ptr [[AVAL_LOC]], ptr [[BVAL_LOC]]) 112; CHECK-NEXT: [[A2VAL_RELOAD:%.*]] = load i32, ptr [[A2VAL_LOC]], align 4 113; CHECK-NEXT: [[B2VAL_RELOAD:%.*]] = load i32, ptr [[B2VAL_LOC]], align 4 114; CHECK-NEXT: [[AVAL_RELOAD:%.*]] = load i32, ptr [[AVAL_LOC]], align 4 115; CHECK-NEXT: [[BVAL_RELOAD:%.*]] = load i32, ptr [[BVAL_LOC]], align 4 116; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[A2VAL_LOC]]) 117; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[B2VAL_LOC]]) 118; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[AVAL_LOC]]) 119; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[BVAL_LOC]]) 120; CHECK-NEXT: br i1 [[TARGETBLOCK]], label [[BLOCK_6:%.*]], label [[BLOCK_7:%.*]] 121; CHECK: block_6: 122; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[AVAL_RELOAD]], [[BVAL_RELOAD]] 123; CHECK-NEXT: ret void 124; CHECK: block_7: 125; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[A2VAL_RELOAD]], [[B2VAL_RELOAD]] 126; CHECK-NEXT: ret void 127; 128; 129; CHECK-LABEL: @outline_outputs2( 130; CHECK-NEXT: entry: 131; CHECK-NEXT: [[BVAL_LOC:%.*]] = alloca i32, align 4 132; CHECK-NEXT: [[AVAL_LOC:%.*]] = alloca i32, align 4 133; CHECK-NEXT: [[B2VAL_LOC:%.*]] = alloca i32, align 4 134; CHECK-NEXT: [[A2VAL_LOC:%.*]] = alloca i32, align 4 135; CHECK-NEXT: [[OUTPUT:%.*]] = alloca i32, align 4 136; CHECK-NEXT: [[RESULT:%.*]] = alloca i32, align 4 137; CHECK-NEXT: [[OUTPUT2:%.*]] = alloca i32, align 4 138; CHECK-NEXT: [[RESULT2:%.*]] = alloca i32, align 4 139; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 140; CHECK-NEXT: [[B:%.*]] = alloca i32, align 4 141; CHECK-NEXT: br label [[BLOCK_2:%.*]] 142; CHECK: block_1: 143; CHECK-NEXT: [[A2:%.*]] = alloca i32, align 4 144; CHECK-NEXT: [[B2:%.*]] = alloca i32, align 4 145; CHECK-NEXT: br label [[BLOCK_2]] 146; CHECK: block_2: 147; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[A2VAL_LOC]]) 148; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[B2VAL_LOC]]) 149; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[AVAL_LOC]]) 150; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[BVAL_LOC]]) 151; CHECK-NEXT: [[TARGETBLOCK:%.*]] = call i1 @outlined_ir_func_0(ptr [[A]], ptr [[B]], ptr [[OUTPUT]], ptr [[RESULT]], ptr [[A2VAL_LOC]], ptr [[B2VAL_LOC]], ptr [[AVAL_LOC]], ptr [[BVAL_LOC]]) 152; CHECK-NEXT: [[A2VAL_RELOAD:%.*]] = load i32, ptr [[A2VAL_LOC]], align 4 153; CHECK-NEXT: [[B2VAL_RELOAD:%.*]] = load i32, ptr [[B2VAL_LOC]], align 4 154; CHECK-NEXT: [[AVAL_RELOAD:%.*]] = load i32, ptr [[AVAL_LOC]], align 4 155; CHECK-NEXT: [[BVAL_RELOAD:%.*]] = load i32, ptr [[BVAL_LOC]], align 4 156; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[A2VAL_LOC]]) 157; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[B2VAL_LOC]]) 158; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[AVAL_LOC]]) 159; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[BVAL_LOC]]) 160; CHECK-NEXT: br i1 [[TARGETBLOCK]], label [[BLOCK_7:%.*]], label [[BLOCK_6:%.*]] 161; CHECK: block_6: 162; CHECK-NEXT: [[DIFF:%.*]] = sub i32 [[A2VAL_RELOAD]], [[B2VAL_RELOAD]] 163; CHECK-NEXT: ret void 164; CHECK: block_7: 165; CHECK-NEXT: [[QUOT:%.*]] = udiv i32 [[AVAL_RELOAD]], [[BVAL_RELOAD]] 166; CHECK-NEXT: ret void 167; 168; 169; CHECK: define internal i1 @outlined_ir_func_0( 170; CHECK-NEXT: newFuncRoot: 171; CHECK-NEXT: br label [[BLOCK_2_TO_OUTLINE:%.*]] 172; CHECK: block_2_to_outline: 173; CHECK-NEXT: [[A2VAL:%.*]] = load i32, ptr [[TMP0:%.*]], align 4 174; CHECK-NEXT: [[B2VAL:%.*]] = load i32, ptr [[TMP1:%.*]], align 4 175; CHECK-NEXT: [[ADD2:%.*]] = add i32 2, [[A2VAL]] 176; CHECK-NEXT: [[MUL2:%.*]] = mul i32 2, [[B2VAL]] 177; CHECK-NEXT: br label [[BLOCK_5:%.*]] 178; CHECK: block_3: 179; CHECK-NEXT: [[AVAL:%.*]] = load i32, ptr [[TMP0]], align 4 180; CHECK-NEXT: [[BVAL:%.*]] = load i32, ptr [[TMP1]], align 4 181; CHECK-NEXT: [[ADD:%.*]] = add i32 2, [[AVAL]] 182; CHECK-NEXT: [[MUL:%.*]] = mul i32 2, [[BVAL]] 183; CHECK-NEXT: br label [[BLOCK_4:%.*]] 184; CHECK: block_4: 185; CHECK-NEXT: store i32 [[ADD]], ptr [[TMP2:%.*]], align 4 186; CHECK-NEXT: store i32 [[MUL]], ptr [[TMP3:%.*]], align 4 187; CHECK-NEXT: br label [[BLOCK_6_EXITSTUB:%.*]] 188; CHECK: block_5: 189; CHECK-NEXT: store i32 [[ADD2]], ptr [[TMP2]], align 4 190; CHECK-NEXT: store i32 [[MUL2]], ptr [[TMP3]], align 4 191; CHECK-NEXT: br label [[BLOCK_7_EXITSTUB:%.*]] 192; CHECK: block_6.exitStub: 193; CHECK-NEXT: store i32 [[AVAL]], ptr [[TMP6:%.*]], align 4 194; CHECK-NEXT: store i32 [[BVAL]], ptr [[TMP7:%.*]], align 4 195; CHECK-NEXT: ret i1 true 196; CHECK: block_7.exitStub: 197; CHECK-NEXT: store i32 [[A2VAL]], ptr [[TMP4:%.*]], align 4 198; CHECK-NEXT: store i32 [[B2VAL]], ptr [[TMP5:%.*]], align 4 199; CHECK-NEXT: ret i1 false 200; 201