xref: /llvm-project/llvm/test/Transforms/IROutliner/illegal-callbr.ll (revision 9dd9575c55c74810675d5de40f56b37dd38fe3c3)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt -S -passes=verify,iroutliner -ir-outlining-no-cost < %s | FileCheck %s
3
4; This test checks that we do not outline callbr instruction since as we do not
5; outline any control flow change instructions.
6
7
8define i32 @function1(i32 %a, i32 %b) {
9; CHECK-LABEL: @function1(
10; CHECK-NEXT:  bb0:
11; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[A:%.*]], 4
12; CHECK-NEXT:    call void @outlined_ir_func_0(i32 [[B:%.*]])
13; CHECK-NEXT:    callbr void asm "xorl $0, $0
14; CHECK-NEXT:    to label [[NORMAL:%.*]] [label %fail1]
15; CHECK:       normal:
16; CHECK-NEXT:    call void @outlined_ir_func_0(i32 [[B]])
17; CHECK-NEXT:    ret i32 0
18; CHECK:       fail1:
19; CHECK-NEXT:    call void @outlined_ir_func_0(i32 [[B]])
20; CHECK-NEXT:    ret i32 0
21;
22bb0:
23  %0 = add i32 %a, 4
24  %1 = add i32 %b, 1
25  %2 = add i32 %b, 1
26  callbr void asm "xorl $0, $0; jmp ${1:l}", "r,!i,~{dirflag},~{fpsr},~{flags}"(i32 %0) to label %normal [label %fail1]
27normal:
28  %3 = add i32 %b, 1
29  %4 = add i32 %b, 1
30  ret i32 0
31fail1:
32  %5 = add i32 %b, 1
33  %6 = add i32 %b, 1
34  ret i32 0
35}
36
37define i32 @function2(i32 %a, i32 %b) {
38; CHECK-LABEL: @function2(
39; CHECK-NEXT:  bb0:
40; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[A:%.*]], 4
41; CHECK-NEXT:    call void @outlined_ir_func_0(i32 [[B:%.*]])
42; CHECK-NEXT:    callbr void asm "xorl $0, $0
43; CHECK-NEXT:    to label [[NORMAL:%.*]] [label %fail1]
44; CHECK:       normal:
45; CHECK-NEXT:    call void @outlined_ir_func_0(i32 [[B]])
46; CHECK-NEXT:    ret i32 0
47; CHECK:       fail1:
48; CHECK-NEXT:    call void @outlined_ir_func_0(i32 [[B]])
49; CHECK-NEXT:    ret i32 0
50;
51bb0:
52  %0 = add i32 %a, 4
53  %1 = add i32 %b, 1
54  %2 = add i32 %b, 1
55  callbr void asm "xorl $0, $0; jmp ${1:l}", "r,!i,~{dirflag},~{fpsr},~{flags}"(i32 %0) to label %normal [label %fail1]
56normal:
57  %3 = add i32 %b, 1
58  %4 = add i32 %b, 1
59  ret i32 0
60fail1:
61  %5 = add i32 %b, 1
62  %6 = add i32 %b, 1
63  ret i32 0
64}
65