1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs 2; RUN: opt -S -passes=verify,iroutliner -ir-outlining-no-cost < %s | FileCheck %s 3 4; Check that differently ordered phi nodes are not matched when merged, instead 5; generating two output paths. 6 7define void @f1() { 8bb1: 9 %0 = add i32 1, 2 10 %1 = add i32 3, 4 11 %2 = add i32 5, 6 12 %3 = add i32 7, 8 13 br i1 true, label %bb2, label %bb5 14bb2: 15 %4 = mul i32 5, 4 16 br label %bb5 17 18placeholder: 19 %a = sub i32 5, 4 20 ret void 21 22bb5: 23 %phinode = phi i32 [%3, %bb1], [%2, %bb2] 24 ret void 25} 26 27define void @f2() { 28bb1: 29 %0 = add i32 1, 2 30 %1 = add i32 3, 4 31 %2 = add i32 5, 6 32 %3 = add i32 7, 8 33 br i1 true, label %bb2, label %bb5 34bb2: 35 %4 = mul i32 5, 4 36 br label %bb5 37 38placeholder: 39 %a = sub i32 5, 4 40 ret void 41 42bb5: 43 %phinode = phi i32 [%2, %bb1], [%3, %bb2] 44 ret void 45} 46; CHECK-LABEL: @f1( 47; CHECK-NEXT: bb1: 48; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 4 49; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[PHINODE_CE_LOC]]) 50; CHECK-NEXT: [[TMP0:%.*]] = call i1 @outlined_ir_func_0(ptr [[PHINODE_CE_LOC]], i32 0) 51; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, ptr [[PHINODE_CE_LOC]], align 4 52; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[PHINODE_CE_LOC]]) 53; CHECK-NEXT: br i1 [[TMP0]], label [[BB5:%.*]], label [[BB1_AFTER_OUTLINE:%.*]] 54; CHECK: bb1_after_outline: 55; CHECK-NEXT: ret void 56; CHECK: bb5: 57; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ] 58; CHECK-NEXT: ret void 59; 60; 61; CHECK-LABEL: @f2( 62; CHECK-NEXT: bb1: 63; CHECK-NEXT: [[PHINODE_CE_LOC:%.*]] = alloca i32, align 4 64; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 -1, ptr [[PHINODE_CE_LOC]]) 65; CHECK-NEXT: [[TMP0:%.*]] = call i1 @outlined_ir_func_0(ptr [[PHINODE_CE_LOC]], i32 1) 66; CHECK-NEXT: [[PHINODE_CE_RELOAD:%.*]] = load i32, ptr [[PHINODE_CE_LOC]], align 4 67; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 -1, ptr [[PHINODE_CE_LOC]]) 68; CHECK-NEXT: br i1 [[TMP0]], label [[BB5:%.*]], label [[BB1_AFTER_OUTLINE:%.*]] 69; CHECK: bb1_after_outline: 70; CHECK-NEXT: ret void 71; CHECK: bb5: 72; CHECK-NEXT: [[PHINODE:%.*]] = phi i32 [ [[PHINODE_CE_RELOAD]], [[BB1:%.*]] ] 73; CHECK-NEXT: ret void 74; 75; 76; CHECK-LABEL: define internal i1 @outlined_ir_func_0( 77; CHECK-NEXT: newFuncRoot: 78; CHECK-NEXT: br label [[BB1_TO_OUTLINE:%.*]] 79; CHECK: bb1_to_outline: 80; CHECK-NEXT: [[TMP2:%.*]] = add i32 1, 2 81; CHECK-NEXT: [[TMP3:%.*]] = add i32 3, 4 82; CHECK-NEXT: [[TMP4:%.*]] = add i32 5, 6 83; CHECK-NEXT: [[TMP5:%.*]] = add i32 7, 8 84; CHECK-NEXT: br i1 true, label [[BB2:%.*]], label [[BB5_SPLIT:%.*]] 85; CHECK: bb2: 86; CHECK-NEXT: [[TMP6:%.*]] = mul i32 5, 4 87; CHECK-NEXT: br label [[BB5_SPLIT]] 88; CHECK: placeholder: 89; CHECK-NEXT: [[A:%.*]] = sub i32 5, 4 90; CHECK-NEXT: br label [[BB1_AFTER_OUTLINE_EXITSTUB:%.*]] 91; CHECK: bb5.split: 92; CHECK-NEXT: [[TMP7:%.*]] = phi i32 [ [[TMP4]], [[BB1_TO_OUTLINE]] ], [ [[TMP5]], [[BB2]] ] 93; CHECK-NEXT: [[PHINODE_CE:%.*]] = phi i32 [ [[TMP5]], [[BB1_TO_OUTLINE]] ], [ [[TMP4]], [[BB2]] ] 94; CHECK-NEXT: br label [[BB5_EXITSTUB:%.*]] 95; CHECK: bb5.exitStub: 96; CHECK-NEXT: switch i32 [[TMP1:%.*]], label [[FINAL_BLOCK_1:%.*]] [ 97; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_0_1:%.*]] 98; CHECK-NEXT: i32 1, label [[OUTPUT_BLOCK_1_1:%.*]] 99; CHECK-NEXT: ] 100; CHECK: bb1_after_outline.exitStub: 101; CHECK-NEXT: switch i32 [[TMP1]], label [[FINAL_BLOCK_0:%.*]] [ 102; CHECK-NEXT: ] 103; CHECK: output_block_0_1: 104; CHECK-NEXT: store i32 [[PHINODE_CE]], ptr [[TMP0:%.*]], align 4 105; CHECK-NEXT: br label [[FINAL_BLOCK_1]] 106; CHECK: output_block_1_1: 107; CHECK-NEXT: store i32 [[TMP7]], ptr [[TMP0]], align 4 108; CHECK-NEXT: br label [[FINAL_BLOCK_1]] 109; CHECK: final_block_0: 110; CHECK-NEXT: ret i1 false 111; CHECK: final_block_1: 112; CHECK-NEXT: ret i1 true 113; 114