xref: /llvm-project/llvm/test/Transforms/EarlyCSE/AMDGPU/memrealtime.ll (revision f0415f2a456d54daaa231c228d2c9f4ef2ce9b89) 
1; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes='early-cse<memssa>' -earlycse-debug-hash < %s | FileCheck %s
2target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
3
4; CHECK-LABEL: @memrealtime(
5; CHECK: call i64 @llvm.amdgcn.s.memrealtime()
6; CHECK: call i64 @llvm.amdgcn.s.memrealtime()
7define amdgpu_kernel void @memrealtime(i64 %cycles) #0 {
8entry:
9  %0 = tail call i64 @llvm.amdgcn.s.memrealtime()
10  %cmp3 = icmp sgt i64 %cycles, 0
11  br i1 %cmp3, label %while.body, label %while.end
12
13while.body:
14  %1 = tail call i64 @llvm.amdgcn.s.memrealtime()
15  %sub = sub nsw i64 %1, %0
16  %cmp = icmp slt i64 %sub, %cycles
17  br i1 %cmp, label %while.body, label %while.end
18
19while.end:
20  ret void
21}
22
23; CHECK-LABEL: @memtime(
24; CHECK: call i64 @llvm.amdgcn.s.memtime()
25; CHECK: call i64 @llvm.amdgcn.s.memtime()
26define amdgpu_kernel void @memtime(i64 %cycles) #0 {
27entry:
28  %0 = tail call i64 @llvm.amdgcn.s.memtime()
29  %cmp3 = icmp sgt i64 %cycles, 0
30  br i1 %cmp3, label %while.body, label %while.end
31
32while.body:
33  %1 = tail call i64 @llvm.amdgcn.s.memtime()
34  %sub = sub nsw i64 %1, %0
35  %cmp = icmp slt i64 %sub, %cycles
36  br i1 %cmp, label %while.body, label %while.end
37
38while.end:
39  ret void
40}
41
42declare i64 @llvm.amdgcn.s.memrealtime()
43declare i64 @llvm.amdgcn.s.memtime()
44