1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3 2; RUN: opt -passes=constraint-elimination -S %s | FileCheck %s 3 4define i32 @test_loop_varying_bound_add_rec() { 5; CHECK-LABEL: define i32 @test_loop_varying_bound_add_rec() { 6; CHECK-NEXT: entry: 7; CHECK-NEXT: br label [[FOR_HEADER:%.*]] 8; CHECK: for.header: 9; CHECK-NEXT: [[IND1:%.*]] = phi i64 [ [[IND1_I:%.*]], [[FOR_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ] 10; CHECK-NEXT: [[IND2:%.*]] = phi i64 [ [[IND2_I:%.*]], [[FOR_LATCH]] ], [ 5, [[ENTRY]] ] 11; CHECK-NEXT: [[REM:%.*]] = srem i64 [[IND2]], 4 12; CHECK-NEXT: [[CMP6:%.*]] = icmp eq i64 [[IND1]], [[REM]] 13; CHECK-NEXT: br i1 [[CMP6]], label [[EXIT1:%.*]], label [[FOR_LATCH]] 14; CHECK: for.latch: 15; CHECK-NEXT: [[IND2_I]] = add i64 [[IND2]], 1 16; CHECK-NEXT: [[IND1_I]] = add i64 [[IND1]], 1 17; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[IND1_I]], 8 18; CHECK-NEXT: br i1 [[COND]], label [[EXIT2:%.*]], label [[FOR_HEADER]] 19; CHECK: exit2: 20; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[REM]], 0 21; CHECK-NEXT: [[RET:%.*]] = zext i1 [[CMP]] to i32 22; CHECK-NEXT: ret i32 [[RET]] 23; CHECK: exit1: 24; CHECK-NEXT: ret i32 0 25; 26entry: 27 br label %for.header 28 29for.header: 30 %ind1 = phi i64 [ %ind1.i, %for.latch ], [ 0, %entry ] 31 %ind2 = phi i64 [ %ind2.i, %for.latch ], [ 5, %entry ] 32 %rem = srem i64 %ind2, 4 33 %cmp6 = icmp eq i64 %ind1, %rem 34 br i1 %cmp6, label %exit1, label %for.latch 35 36for.latch: 37 %ind2.i = add i64 %ind2, 1 38 %ind1.i = add i64 %ind1, 1 39 %cond = icmp eq i64 %ind1.i, 8 40 br i1 %cond, label %exit2, label %for.header 41 42exit2: 43 %cmp = icmp eq i64 %rem, 0 44 %ret = zext i1 %cmp to i32 45 ret i32 %ret 46 47exit1: 48 ret i32 0 49} 50 51declare i64 @callee() 52 53define i32 @test_loop_varying_bound_call() { 54; CHECK-LABEL: define i32 @test_loop_varying_bound_call() { 55; CHECK-NEXT: entry: 56; CHECK-NEXT: br label [[FOR_HEADER:%.*]] 57; CHECK: for.header: 58; CHECK-NEXT: [[IND1:%.*]] = phi i64 [ [[IND1_I:%.*]], [[FOR_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ] 59; CHECK-NEXT: [[VAL:%.*]] = call i64 @callee() 60; CHECK-NEXT: [[CMP6:%.*]] = icmp eq i64 [[IND1]], [[VAL]] 61; CHECK-NEXT: br i1 [[CMP6]], label [[EXIT1:%.*]], label [[FOR_LATCH]] 62; CHECK: for.latch: 63; CHECK-NEXT: [[IND1_I]] = add i64 [[IND1]], 1 64; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[IND1_I]], 8 65; CHECK-NEXT: br i1 [[COND]], label [[EXIT2:%.*]], label [[FOR_HEADER]] 66; CHECK: exit2: 67; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[VAL]], 0 68; CHECK-NEXT: [[RET:%.*]] = zext i1 [[CMP]] to i32 69; CHECK-NEXT: ret i32 [[RET]] 70; CHECK: exit1: 71; CHECK-NEXT: ret i32 0 72; 73entry: 74 br label %for.header 75 76for.header: 77 %ind1 = phi i64 [ %ind1.i, %for.latch ], [ 0, %entry ] 78 %val = call i64 @callee() 79 %cmp6 = icmp eq i64 %ind1, %val 80 br i1 %cmp6, label %exit1, label %for.latch 81 82for.latch: 83 %ind1.i = add i64 %ind1, 1 84 %cond = icmp eq i64 %ind1.i, 8 85 br i1 %cond, label %exit2, label %for.header 86 87exit2: 88 %cmp = icmp eq i64 %val, 0 89 %ret = zext i1 %cmp to i32 90 ret i32 %ret 91 92exit1: 93 ret i32 0 94} 95