xref: /llvm-project/llvm/test/Transforms/AtomicExpand/AMDGPU/unaligned-atomic.ll (revision fe42e72db29e48aa81eac2aa922afd90a7f01517) 
1; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=atomic-expand %s 2>&1 | FileCheck --check-prefix=GCN %s
2
3define i32 @atomic_load_global_align1(ptr addrspace(1) %ptr) {
4; GCN-LABEL: @atomic_load_global_align1(
5; GCN-NEXT:    [[TMP2:%.*]] = addrspacecast ptr addrspace(1) [[PTR:%.*]] to ptr
6; GCN-NEXT:    [[TMP3:%.*]] = alloca i32, align 4, addrspace(5)
7; GCN-NEXT:    call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP3]])
8; GCN-NEXT:    call void @__atomic_load(i64 4, ptr [[TMP2]], ptr addrspace(5) [[TMP3]], i32 5)
9; GCN-NEXT:    [[TMP5:%.*]] = load i32, ptr addrspace(5) [[TMP3]], align 4
10; GCN-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP3]])
11; GCN-NEXT:    ret i32 [[TMP5]]
12;
13  %val = load atomic i32, ptr addrspace(1) %ptr  seq_cst, align 1
14  ret i32 %val
15}
16
17define void @atomic_store_global_align1(ptr addrspace(1) %ptr, i32 %val) {
18; GCN-LABEL: @atomic_store_global_align1(
19; GCN-NEXT:    [[TMP2:%.*]] = addrspacecast ptr addrspace(1) [[PTR:%.*]] to ptr
20; GCN-NEXT:    [[TMP3:%.*]] = alloca i32, align 4, addrspace(5)
21; GCN-NEXT:    call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP3]])
22; GCN-NEXT:    store i32 [[VAL:%.*]], ptr addrspace(5) [[TMP3]], align 4
23; GCN-NEXT:    call void @__atomic_store(i64 4, ptr [[TMP2]], ptr addrspace(5) [[TMP3]], i32 0)
24; GCN-NEXT:    call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP3]])
25; GCN-NEXT:    ret void
26;
27  store atomic i32 %val, ptr addrspace(1) %ptr monotonic, align 1
28  ret void
29}
30