1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes 2; RUN: opt -S -passes=argpromotion < %s | FileCheck %s 3; Test that we only promote arguments when the caller/callee have compatible 4; function attrubtes. 5 6target triple = "x86_64-unknown-linux-gnu" 7 8; This should promote 9define internal fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(ptr %arg, ptr readonly %arg1) #0 { 10; CHECK-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512 11; CHECK-SAME: (ptr [[ARG:%.*]], <8 x i64> [[ARG1_VAL:%.*]]) 12; CHECK-NEXT: bb: 13; CHECK-NEXT: store <8 x i64> [[ARG1_VAL]], ptr [[ARG]] 14; CHECK-NEXT: ret void 15; 16bb: 17 %tmp = load <8 x i64>, ptr %arg1 18 store <8 x i64> %tmp, ptr %arg 19 ret void 20} 21 22define void @avx512_legal512_prefer512_call_avx512_legal512_prefer512(ptr %arg) #0 { 23; CHECK-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer512 24; CHECK-SAME: (ptr [[ARG:%.*]]) 25; CHECK-NEXT: bb: 26; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 27; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 28; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false) 29; CHECK-NEXT: [[TMP_VAL:%.*]] = load <8 x i64>, ptr [[TMP]] 30; CHECK-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(ptr [[TMP2]], <8 x i64> [[TMP_VAL]]) 31; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 32 32; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2 33; CHECK-NEXT: ret void 34; 35bb: 36 %tmp = alloca <8 x i64>, align 32 37 %tmp2 = alloca <8 x i64>, align 32 38 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false) 39 call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer512(ptr %tmp2, ptr %tmp) 40 %tmp4 = load <8 x i64>, ptr %tmp2, align 32 41 store <8 x i64> %tmp4, ptr %arg, align 2 42 ret void 43} 44 45; This should promote 46define internal fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(ptr %arg, ptr readonly %arg1) #1 { 47; CHECK-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256 48; CHECK-SAME: (ptr [[ARG:%.*]], <8 x i64> [[ARG1_VAL:%.*]]) 49; CHECK-NEXT: bb: 50; CHECK-NEXT: store <8 x i64> [[ARG1_VAL]], ptr [[ARG]] 51; CHECK-NEXT: ret void 52; 53bb: 54 %tmp = load <8 x i64>, ptr %arg1 55 store <8 x i64> %tmp, ptr %arg 56 ret void 57} 58 59define void @avx512_legal512_prefer256_call_avx512_legal512_prefer256(ptr %arg) #1 { 60; CHECK-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer256 61; CHECK-SAME: (ptr [[ARG:%.*]]) 62; CHECK-NEXT: bb: 63; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 64; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 65; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false) 66; CHECK-NEXT: [[TMP_VAL:%.*]] = load <8 x i64>, ptr [[TMP]] 67; CHECK-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(ptr [[TMP2]], <8 x i64> [[TMP_VAL]]) 68; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 32 69; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2 70; CHECK-NEXT: ret void 71; 72bb: 73 %tmp = alloca <8 x i64>, align 32 74 %tmp2 = alloca <8 x i64>, align 32 75 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false) 76 call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer256(ptr %tmp2, ptr %tmp) 77 %tmp4 = load <8 x i64>, ptr %tmp2, align 32 78 store <8 x i64> %tmp4, ptr %arg, align 2 79 ret void 80} 81 82; This should promote 83define internal fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(ptr %arg, ptr readonly %arg1) #1 { 84; CHECK-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256 85; CHECK-SAME: (ptr [[ARG:%.*]], <8 x i64> [[ARG1_VAL:%.*]]) 86; CHECK-NEXT: bb: 87; CHECK-NEXT: store <8 x i64> [[ARG1_VAL]], ptr [[ARG]] 88; CHECK-NEXT: ret void 89; 90bb: 91 %tmp = load <8 x i64>, ptr %arg1 92 store <8 x i64> %tmp, ptr %arg 93 ret void 94} 95 96define void @avx512_legal512_prefer512_call_avx512_legal512_prefer256(ptr %arg) #0 { 97; CHECK-LABEL: define {{[^@]+}}@avx512_legal512_prefer512_call_avx512_legal512_prefer256 98; CHECK-SAME: (ptr [[ARG:%.*]]) 99; CHECK-NEXT: bb: 100; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 101; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 102; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false) 103; CHECK-NEXT: [[TMP_VAL:%.*]] = load <8 x i64>, ptr [[TMP]] 104; CHECK-NEXT: call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(ptr [[TMP2]], <8 x i64> [[TMP_VAL]]) 105; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 32 106; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2 107; CHECK-NEXT: ret void 108; 109bb: 110 %tmp = alloca <8 x i64>, align 32 111 %tmp2 = alloca <8 x i64>, align 32 112 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false) 113 call fastcc void @callee_avx512_legal512_prefer512_call_avx512_legal512_prefer256(ptr %tmp2, ptr %tmp) 114 %tmp4 = load <8 x i64>, ptr %tmp2, align 32 115 store <8 x i64> %tmp4, ptr %arg, align 2 116 ret void 117} 118 119; This should promote 120define internal fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(ptr %arg, ptr readonly %arg1) #0 { 121; CHECK-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512 122; CHECK-SAME: (ptr [[ARG:%.*]], <8 x i64> [[ARG1_VAL:%.*]]) 123; CHECK-NEXT: bb: 124; CHECK-NEXT: store <8 x i64> [[ARG1_VAL]], ptr [[ARG]] 125; CHECK-NEXT: ret void 126; 127bb: 128 %tmp = load <8 x i64>, ptr %arg1 129 store <8 x i64> %tmp, ptr %arg 130 ret void 131} 132 133define void @avx512_legal512_prefer256_call_avx512_legal512_prefer512(ptr %arg) #1 { 134; CHECK-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal512_prefer512 135; CHECK-SAME: (ptr [[ARG:%.*]]) 136; CHECK-NEXT: bb: 137; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 138; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 139; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false) 140; CHECK-NEXT: [[TMP_VAL:%.*]] = load <8 x i64>, ptr [[TMP]] 141; CHECK-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(ptr [[TMP2]], <8 x i64> [[TMP_VAL]]) 142; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 32 143; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2 144; CHECK-NEXT: ret void 145; 146bb: 147 %tmp = alloca <8 x i64>, align 32 148 %tmp2 = alloca <8 x i64>, align 32 149 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false) 150 call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal512_prefer512(ptr %tmp2, ptr %tmp) 151 %tmp4 = load <8 x i64>, ptr %tmp2, align 32 152 store <8 x i64> %tmp4, ptr %arg, align 2 153 ret void 154} 155 156; This should not promote 157define internal fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr %arg, ptr readonly %arg1) #1 { 158; CHECK-LABEL: define {{[^@]+}}@callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256 159; CHECK-SAME: (ptr [[ARG:%.*]], ptr readonly [[ARG1:%.*]]) 160; CHECK-NEXT: bb: 161; CHECK-NEXT: [[TMP:%.*]] = load <8 x i64>, ptr [[ARG1]] 162; CHECK-NEXT: store <8 x i64> [[TMP]], ptr [[ARG]] 163; CHECK-NEXT: ret void 164; 165bb: 166 %tmp = load <8 x i64>, ptr %arg1 167 store <8 x i64> %tmp, ptr %arg 168 ret void 169} 170 171define void @avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr %arg) #2 { 172; CHECK-LABEL: define {{[^@]+}}@avx512_legal256_prefer256_call_avx512_legal512_prefer256 173; CHECK-SAME: (ptr [[ARG:%.*]]) 174; CHECK-NEXT: bb: 175; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 176; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 177; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false) 178; CHECK-NEXT: call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr [[TMP2]], ptr [[TMP]]) 179; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 32 180; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2 181; CHECK-NEXT: ret void 182; 183bb: 184 %tmp = alloca <8 x i64>, align 32 185 %tmp2 = alloca <8 x i64>, align 32 186 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false) 187 call fastcc void @callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr %tmp2, ptr %tmp) 188 %tmp4 = load <8 x i64>, ptr %tmp2, align 32 189 store <8 x i64> %tmp4, ptr %arg, align 2 190 ret void 191} 192 193; This should not promote 194define internal fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr %arg, ptr readonly %arg1) #2 { 195; CHECK-LABEL: define {{[^@]+}}@callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256 196; CHECK-SAME: (ptr [[ARG:%.*]], ptr readonly [[ARG1:%.*]]) 197; CHECK-NEXT: bb: 198; CHECK-NEXT: [[TMP:%.*]] = load <8 x i64>, ptr [[ARG1]] 199; CHECK-NEXT: store <8 x i64> [[TMP]], ptr [[ARG]] 200; CHECK-NEXT: ret void 201; 202bb: 203 %tmp = load <8 x i64>, ptr %arg1 204 store <8 x i64> %tmp, ptr %arg 205 ret void 206} 207 208define void @avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr %arg) #1 { 209; CHECK-LABEL: define {{[^@]+}}@avx512_legal512_prefer256_call_avx512_legal256_prefer256 210; CHECK-SAME: (ptr [[ARG:%.*]]) 211; CHECK-NEXT: bb: 212; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 213; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 214; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false) 215; CHECK-NEXT: call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr [[TMP2]], ptr [[TMP]]) 216; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 32 217; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2 218; CHECK-NEXT: ret void 219; 220bb: 221 %tmp = alloca <8 x i64>, align 32 222 %tmp2 = alloca <8 x i64>, align 32 223 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false) 224 call fastcc void @callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr %tmp2, ptr %tmp) 225 %tmp4 = load <8 x i64>, ptr %tmp2, align 32 226 store <8 x i64> %tmp4, ptr %arg, align 2 227 ret void 228} 229 230; This should promote 231define internal fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(ptr %arg, ptr readonly %arg1) #3 { 232; CHECK-LABEL: define {{[^@]+}}@callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256 233; CHECK-SAME: (ptr [[ARG:%.*]], <8 x i64> [[ARG1_VAL:%.*]]) 234; CHECK-NEXT: bb: 235; CHECK-NEXT: store <8 x i64> [[ARG1_VAL]], ptr [[ARG]] 236; CHECK-NEXT: ret void 237; 238bb: 239 %tmp = load <8 x i64>, ptr %arg1 240 store <8 x i64> %tmp, ptr %arg 241 ret void 242} 243 244define void @avx2_legal256_prefer256_call_avx2_legal512_prefer256(ptr %arg) #4 { 245; CHECK-LABEL: define {{[^@]+}}@avx2_legal256_prefer256_call_avx2_legal512_prefer256 246; CHECK-SAME: (ptr [[ARG:%.*]]) 247; CHECK-NEXT: bb: 248; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 249; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 250; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false) 251; CHECK-NEXT: [[TMP_VAL:%.*]] = load <8 x i64>, ptr [[TMP]] 252; CHECK-NEXT: call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(ptr [[TMP2]], <8 x i64> [[TMP_VAL]]) 253; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 32 254; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2 255; CHECK-NEXT: ret void 256; 257bb: 258 %tmp = alloca <8 x i64>, align 32 259 %tmp2 = alloca <8 x i64>, align 32 260 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false) 261 call fastcc void @callee_avx2_legal256_prefer256_call_avx2_legal512_prefer256(ptr %tmp2, ptr %tmp) 262 %tmp4 = load <8 x i64>, ptr %tmp2, align 32 263 store <8 x i64> %tmp4, ptr %arg, align 2 264 ret void 265} 266 267; This should promote 268define internal fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(ptr %arg, ptr readonly %arg1) #4 { 269; CHECK-LABEL: define {{[^@]+}}@callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256 270; CHECK-SAME: (ptr [[ARG:%.*]], <8 x i64> [[ARG1_VAL:%.*]]) 271; CHECK-NEXT: bb: 272; CHECK-NEXT: store <8 x i64> [[ARG1_VAL]], ptr [[ARG]] 273; CHECK-NEXT: ret void 274; 275bb: 276 %tmp = load <8 x i64>, ptr %arg1 277 store <8 x i64> %tmp, ptr %arg 278 ret void 279} 280 281define void @avx2_legal512_prefer256_call_avx2_legal256_prefer256(ptr %arg) #3 { 282; CHECK-LABEL: define {{[^@]+}}@avx2_legal512_prefer256_call_avx2_legal256_prefer256 283; CHECK-SAME: (ptr [[ARG:%.*]]) 284; CHECK-NEXT: bb: 285; CHECK-NEXT: [[TMP:%.*]] = alloca <8 x i64>, align 32 286; CHECK-NEXT: [[TMP2:%.*]] = alloca <8 x i64>, align 32 287; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false) 288; CHECK-NEXT: [[TMP_VAL:%.*]] = load <8 x i64>, ptr [[TMP]] 289; CHECK-NEXT: call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(ptr [[TMP2]], <8 x i64> [[TMP_VAL]]) 290; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i64>, ptr [[TMP2]], align 32 291; CHECK-NEXT: store <8 x i64> [[TMP4]], ptr [[ARG]], align 2 292; CHECK-NEXT: ret void 293; 294bb: 295 %tmp = alloca <8 x i64>, align 32 296 %tmp2 = alloca <8 x i64>, align 32 297 call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false) 298 call fastcc void @callee_avx2_legal512_prefer256_call_avx2_legal256_prefer256(ptr %tmp2, ptr %tmp) 299 %tmp4 = load <8 x i64>, ptr %tmp2, align 32 300 store <8 x i64> %tmp4, ptr %arg, align 2 301 ret void 302} 303 304; If the arguments are scalar, its ok to promote. 305define internal i32 @scalar_callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr %X, ptr %Y) #2 { 306; CHECK-LABEL: define {{[^@]+}}@scalar_callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256 307; CHECK-SAME: (i32 [[X_VAL:%.*]], i32 [[Y_VAL:%.*]]) 308; CHECK-NEXT: [[C:%.*]] = add i32 [[X_VAL]], [[Y_VAL]] 309; CHECK-NEXT: ret i32 [[C]] 310; 311 %A = load i32, ptr %X 312 %B = load i32, ptr %Y 313 %C = add i32 %A, %B 314 ret i32 %C 315} 316 317define i32 @scalar_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr %B) #2 { 318; CHECK-LABEL: define {{[^@]+}}@scalar_avx512_legal256_prefer256_call_avx512_legal512_prefer256 319; CHECK-SAME: (ptr [[B:%.*]]) 320; CHECK-NEXT: [[A:%.*]] = alloca i32 321; CHECK-NEXT: store i32 1, ptr [[A]] 322; CHECK-NEXT: [[A_VAL:%.*]] = load i32, ptr [[A]] 323; CHECK-NEXT: [[B_VAL:%.*]] = load i32, ptr [[B]] 324; CHECK-NEXT: [[C:%.*]] = call i32 @scalar_callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(i32 [[A_VAL]], i32 [[B_VAL]]) 325; CHECK-NEXT: ret i32 [[C]] 326; 327 %A = alloca i32 328 store i32 1, ptr %A 329 %C = call i32 @scalar_callee_avx512_legal256_prefer256_call_avx512_legal512_prefer256(ptr %A, ptr %B) 330 ret i32 %C 331} 332 333; If the arguments are scalar, its ok to promote. 334define internal i32 @scalar_callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr %X, ptr %Y) #2 { 335; CHECK-LABEL: define {{[^@]+}}@scalar_callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256 336; CHECK-SAME: (i32 [[X_VAL:%.*]], i32 [[Y_VAL:%.*]]) 337; CHECK-NEXT: [[C:%.*]] = add i32 [[X_VAL]], [[Y_VAL]] 338; CHECK-NEXT: ret i32 [[C]] 339; 340 %A = load i32, ptr %X 341 %B = load i32, ptr %Y 342 %C = add i32 %A, %B 343 ret i32 %C 344} 345 346define i32 @scalar_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr %B) #2 { 347; CHECK-LABEL: define {{[^@]+}}@scalar_avx512_legal512_prefer256_call_avx512_legal256_prefer256 348; CHECK-SAME: (ptr [[B:%.*]]) 349; CHECK-NEXT: [[A:%.*]] = alloca i32 350; CHECK-NEXT: store i32 1, ptr [[A]] 351; CHECK-NEXT: [[A_VAL:%.*]] = load i32, ptr [[A]] 352; CHECK-NEXT: [[B_VAL:%.*]] = load i32, ptr [[B]] 353; CHECK-NEXT: [[C:%.*]] = call i32 @scalar_callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(i32 [[A_VAL]], i32 [[B_VAL]]) 354; CHECK-NEXT: ret i32 [[C]] 355; 356 %A = alloca i32 357 store i32 1, ptr %A 358 %C = call i32 @scalar_callee_avx512_legal512_prefer256_call_avx512_legal256_prefer256(ptr %A, ptr %B) 359 ret i32 %C 360} 361 362; Function Attrs: argmemonly nounwind 363declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1) #5 364 365attributes #0 = { inlinehint norecurse nounwind uwtable "target-features"="+avx512vl" "min-legal-vector-width"="512" "prefer-vector-width"="512" } 366attributes #1 = { inlinehint norecurse nounwind uwtable "target-features"="+avx512vl" "min-legal-vector-width"="512" "prefer-vector-width"="256" } 367attributes #2 = { inlinehint norecurse nounwind uwtable "target-features"="+avx512vl" "min-legal-vector-width"="256" "prefer-vector-width"="256" } 368attributes #3 = { inlinehint norecurse nounwind uwtable "target-features"="+avx2" "min-legal-vector-width"="512" "prefer-vector-width"="256" } 369attributes #4 = { inlinehint norecurse nounwind uwtable "target-features"="+avx2" "min-legal-vector-width"="256" "prefer-vector-width"="256" } 370attributes #5 = { argmemonly nounwind } 371