xref: /llvm-project/llvm/test/TableGen/riscv-target-def.td (revision 4da960b898f404d91109b50d423c3db400b4e9a8) 
1// RUN: llvm-tblgen -gen-riscv-target-def -I %p/../../include %s | FileCheck %s
2
3include "llvm/Target/Target.td"
4
5class RISCVExtension<string name, int major, int minor, string desc,
6                     list<SubtargetFeature> implies = [],
7                     string fieldname = !subst("Feature", "Has", NAME),
8                     string value = "true">
9    : SubtargetFeature<name, fieldname, value, desc, implies> {
10  int MajorVersion = major;
11  int MinorVersion = minor;
12  bit Experimental = false;
13}
14
15class RISCVExtensionBitmask<bits<3> groupID, int bitPos> {
16  int GroupID = groupID;
17  int BitPos = bitPos;
18}
19
20class RISCVExperimentalExtension<string name, int major, int minor, string desc,
21                                 list<RISCVExtension> implies = [],
22                                 string fieldname = !subst("Feature", "Has", NAME),
23                                 string value = "true">
24    : RISCVExtension<"experimental-"#name, major, minor, desc, implies,
25                     fieldname, value> {
26  let Experimental = true;
27}
28
29def FeatureStdExtI
30    : RISCVExtension<"i", 2, 1,
31                     "'I' (Base Integer Instruction Set)">,
32      RISCVExtensionBitmask<0, 8>;
33
34def FeatureStdExtZicsr
35    : RISCVExtension<"zicsr", 2, 0,
36                     "'zicsr' (CSRs)">;
37
38def FeatureStdExtZifencei
39    : RISCVExtension<"zifencei", 2, 0,
40                     "'Zifencei' (fence.i)">;
41
42def FeatureStdExtF
43    : RISCVExtension<"f", 2, 2,
44                     "'F' (Single-Precision Floating-Point)",
45                     [FeatureStdExtZicsr]>,
46      RISCVExtensionBitmask<0, 5>;
47
48def FeatureStdExtZidummy
49    : RISCVExperimentalExtension<"zidummy", 0, 1,
50                                 "Dummy">;
51
52def Feature32Bit
53    : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
54def Feature64Bit
55    : SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
56
57// Dummy feature that isn't an extension.
58def FeatureDummy
59    : SubtargetFeature<"dummy", "Dummy", "true", "Dummy">;
60
61class RISCVProfile<string name, list<SubtargetFeature> features>
62    : SubtargetFeature<name, "Is" # NAME, "true",
63                       "RISC-V " # name # " profile", features> {
64  bit Experimental = false;
65}
66class RISCVExperimentalProfile<string name, list<SubtargetFeature> features>
67    : RISCVProfile<"experimental-"#name, features> {
68  let Experimental = true;
69}
70
71def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>;
72def RVI20U64 : RISCVProfile<"rvi20u64", [Feature64Bit, FeatureStdExtI]>;
73def ProfileDummy : RISCVProfile<"dummy", [Feature64Bit, FeatureStdExtI,
74                                          FeatureStdExtF, FeatureStdExtZidummy]>;
75def RVI99U64 : RISCVExperimentalProfile<"rvi99u64", [Feature64Bit, FeatureStdExtI]>;
76
77class RISCVProcessorModel<string n,
78                          SchedMachineModel m,
79                          list<SubtargetFeature> f,
80                          list<SubtargetFeature> tunef = [],
81                          string default_march = "">
82    :  ProcessorModel<n, m, f, tunef> {
83  string DefaultMarch = default_march;
84  int MVendorID = 0;
85  int MArchID = 0;
86  int MImpID = 0;
87}
88
89class RISCVTuneProcessorModel<string n,
90                              SchedMachineModel m,
91                              list<SubtargetFeature> tunef = [],
92                              list<SubtargetFeature> f = []>
93    : ProcessorModel<n, m, f,tunef>;
94
95def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
96                                       NoSchedModel,
97                                       [Feature32Bit,
98                                        FeatureStdExtI]>;
99def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
100                                       NoSchedModel,
101                                       [Feature64Bit,
102                                        FeatureStdExtI]>;
103def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>;
104
105
106def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
107                                      NoSchedModel,
108                                      [Feature32Bit,
109                                       FeatureStdExtI,
110                                       FeatureStdExtZifencei,
111                                       FeatureStdExtZicsr,
112                                       FeatureStdExtZidummy,
113                                       FeatureDummy]>;
114def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
115                                      NoSchedModel,
116                                      [Feature64Bit,
117                                       FeatureStdExtI,
118                                       FeatureStdExtZifencei,
119                                       FeatureStdExtZicsr,
120                                       FeatureStdExtZidummy,
121                                       FeatureDummy]>;
122def ROCKET : RISCVTuneProcessorModel<"rocket",
123                                     NoSchedModel>;
124
125// CHECK:      #ifdef GET_SUPPORTED_EXTENSIONS
126// CHECK-NEXT: #undef GET_SUPPORTED_EXTENSIONS
127
128// CHECK:      static const RISCVSupportedExtension SupportedExtensions[] = {
129// CHECK-NEXT:     {"f", {2, 2}},
130// CHECK-NEXT:     {"i", {2, 1}},
131// CHECK-NEXT:     {"zicsr", {2, 0}},
132// CHECK-NEXT:     {"zifencei", {2, 0}},
133// CHECK-NEXT: };
134
135// CHECK:      static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
136// CHECK-NEXT:     {"zidummy", {0, 1}},
137// CHECK-NEXT: };
138
139// CHECK:      #endif // GET_SUPPORTED_EXTENSIONS
140
141// CHECK:      #ifdef GET_IMPLIED_EXTENSIONS
142// CHECK-NEXT: #undef GET_IMPLIED_EXTENSIONS
143
144// CHECK:      static constexpr ImpliedExtsEntry ImpliedExts[] = {
145// CHECK-NEXT:       { {"f"}, "zicsr"},
146// CHECK-NEXT: };
147
148// CHECK:      #endif // GET_IMPLIED_EXTENSIONS
149
150// CHECK:      #ifdef GET_SUPPORTED_PROFILES
151// CHECK-NEXT: #undef GET_SUPPORTED_PROFILES
152
153// CHECK:      static constexpr RISCVProfile SupportedProfiles[] = {
154// CHECK-NEXT:     {"dummy","rv64i2p1_f2p2_zidummy0p1"},
155// CHECK-NEXT:     {"rvi20u32","rv32i2p1"},
156// CHECK-NEXT:     {"rvi20u64","rv64i2p1"},
157// CHECK-NEXT: };
158
159// CHECK:      static constexpr RISCVProfile SupportedExperimentalProfiles[] = {
160// CHECK-NEXT:     {"rvi99u64","rv64i2p1"},
161// CHECK-NEXT: };
162
163// CHECK:      #endif // GET_SUPPORTED_PROFILES
164
165// CHECK:      #ifndef PROC
166// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)
167// CHECK-NEXT: #endif
168
169// CHECK:      PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
170// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
171// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
172// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
173
174// CHECK: #undef PROC
175
176// CHECK:      #ifndef TUNE_PROC
177// CHECK-NEXT: #define TUNE_PROC(ENUM, NAME)
178// CHECK-NEXT: #endif
179
180// CHECK: TUNE_PROC(GENERIC, "generic")
181// CHECK-NEXT: TUNE_PROC(ROCKET, "rocket")
182
183// CHECK: #undef TUNE_PROC
184
185// CHECK: #ifdef GET_RISCVExtensionBitmaskTable_IMPL
186// CHECK-NEXT: static const RISCVExtensionBitmask ExtensionBitmask[]={
187// CHECK-NEXT:     {"f", 0, 5ULL},
188// CHECK-NEXT:     {"i", 0, 8ULL},
189// CHECK-NEXT: };
190// CHECK-NEXT: #endif
191