xref: /llvm-project/llvm/test/TableGen/pseudo-inst-expansion.td (revision 61fa35c3f7e8d06130fbee13d5620e8c3258ec5c) 
1// RUN: llvm-tblgen -gen-pseudo-lowering -I %p/../../include %s | FileCheck %s
2
3include "llvm/Target/Target.td"
4
5def TestTargetInstrInfo : InstrInfo;
6
7def TestTarget : Target {
8  let InstructionSet = TestTargetInstrInfo;
9}
10
11def REG : Register<"REG">;
12def GPR : RegisterClass<"TestTarget", [i32], 32, (add REG)>;
13
14class SysReg<bits<12> op> {
15  bits<12> Encoding = op;
16}
17def SR : SysReg<0b111100001111>;
18
19class Pseudo<dag outs, dag ins, list<dag> pattern>
20    : Instruction {
21  dag OutOperandList = outs;
22  dag InOperandList = ins;
23  let Pattern = pattern;
24  let isPseudo = 1;
25}
26
27def INSTR : Instruction {
28  let OutOperandList = (outs GPR:$rd);
29  let InOperandList = (ins i32imm:$val);
30  let Pattern = [];
31}
32
33def PSEUDO : Pseudo<(outs GPR:$rd), (ins),
34                    [(set GPR:$rd, (i32 SR.Encoding))]>,
35             PseudoInstExpansion<(INSTR GPR:$rd, SR.Encoding)>;
36
37// CHECK: .addOperand(MCOperand::createImm(3855));
38