1// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s 2 3// Check that getOperandType has the expected info in it 4 5include "llvm/Target/Target.td" 6 7def archInstrInfo : InstrInfo { } 8 9def arch : Target { 10 let InstructionSet = archInstrInfo; 11} 12 13def Reg : Register<"reg">; 14def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>; 15 16def OpA : Operand<i32>; 17def OpB : Operand<i32>; 18 19def RegOp : RegisterOperand<RegClass>; 20 21def InstA : Instruction { 22 let Size = 1; 23 let OutOperandList = (outs OpA:$a); 24 let InOperandList = (ins OpB:$b, i32imm:$c); 25 field bits<8> Inst; 26 field bits<8> SoftFail = 0; 27 let Namespace = "MyNamespace"; 28} 29 30def InstB : Instruction { 31 let Size = 1; 32 let OutOperandList = (outs i32imm:$d); 33 let InOperandList = (ins unknown:$x); 34 field bits<8> Inst; 35 field bits<8> SoftFail = 0; 36 let Namespace = "MyNamespace"; 37} 38 39def InstC : Instruction { 40 let Size = 1; 41 let OutOperandList = (outs RegClass:$d); 42 let InOperandList = (ins RegOp:$x); 43 field bits<8> Inst; 44 field bits<8> SoftFail = 0; 45 let Namespace = "MyNamespace"; 46} 47 48// CHECK: #ifdef GET_INSTRINFO_OPERAND_TYPE 49// CHECK: static const uint{{.*}}_t Offsets[] = { 50// CHECK: static const {{.*}} OpcodeOperandTypes[] = { 51// CHECK: /* InstA */ 52// CHECK-NEXT: OpA, OpB, i32imm, 53// CHECK-NEXT: /* InstB */ 54// CHECK-NEXT: i32imm, -1, 55// CHECK-NEXT: /* InstC */ 56// CHECK-NEXT: RegClass, RegOp, 57// CHECK: #endif // GET_INSTRINFO_OPERAND_TYPE 58