1// RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s -o - 2>%t 2// RUN: FileCheck %s < %t 3 4include "llvm/Target/Target.td" 5 6def MyTargetISA : InstrInfo; 7def MyTarget : Target { let InstructionSet = MyTargetISA; } 8 9def R0 : Register<"r0"> { let Namespace = "MyTarget"; } 10def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>; 11 12class I<dag OOps, dag IOps, list<dag> Pat> 13 : Instruction { 14 let Namespace = "MyTarget"; 15 let OutOperandList = OOps; 16 let InOperandList = IOps; 17 let Pattern = Pat; 18 bits<32> Inst; 19 bits<32> SoftFail; 20} 21 22def A : I<(outs GPR32:$dst), (ins GPR32:$src1), []> { 23 let Size = 4; 24 let Inst{31...0} = 0; 25} 26def B : I<(outs GPR32:$dst), (ins GPR32:$src1), []> { 27 let Size = 4; 28 let Inst{31...0} = 0; 29} 30 31// CHECK: Decoding Conflict: 32// CHECK: 00000000000000000000000000000000 33// CHECK: ................................ 34// CHECK: A 00000000000000000000000000000000 35// CHECK: B 00000000000000000000000000000000 36