1// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s 2 3// Make sure that ReadAdvance entries are correctly processed. 4// Not all ProcReadAdvance definitions implicitly inherit from SchedRead. 5// Some ProcReadAdvances are subclasses of ReadAdvance. 6 7include "llvm/Target/Target.td" 8 9def MyTarget : Target; 10 11let OutOperandList = (outs), InOperandList = (ins) in { 12 def Inst_A : Instruction; 13 def Inst_B : Instruction; 14 def Inst_C : Instruction; 15 16} 17 18let CompleteModel = 0 in { 19 def SchedModel_A: SchedMachineModel; 20} 21 22def Read_D : SchedRead; 23 24// CHECK: extern const llvm::MCWriteLatencyEntry MyTargetWriteLatencyTable[] = { 25// CHECK-NEXT: { 0, 0}, // Invalid 26// CHECK-NEXT: { 1, 0}, // #1 Write_A_Write_C 27// CHECK-NEXT: { 1, 2} // #2 Write_B 28// CHECK-NEXT: }; // MyTargetWriteLatencyTable 29 30// CHECK: extern const llvm::MCReadAdvanceEntry MyTargetReadAdvanceTable[] = { 31// CHECK-NEXT: {0, 0, 0}, // Invalid 32// CHECK-NEXT: {0, 2, 1} // #1 33// CHECK-NEXT: }; // MyTargetReadAdvanceTable 34 35// CHECK: static const llvm::MCSchedClassDesc SchedModel_ASchedClasses[] = { 36// CHECK-NEXT: {DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, 37// CHECK-NEXT: {DBGFIELD("Inst_A") 1, false, false, false, 0, 0, 1, 1, 0, 0}, // #1 38// CHECK-NEXT: {DBGFIELD("Inst_B") 1, false, false, false, 0, 0, 2, 1, 0, 0}, // #2 39// CHECK-NEXT: {DBGFIELD("Inst_C") 1, false, false, false, 0, 0, 1, 1, 1, 1}, // #3 40// CHECK-NEXT: }; // SchedModel_ASchedClasses 41 42let SchedModel = SchedModel_A in { 43 def Write_A : SchedWriteRes<[]>; 44 def Write_B : SchedWriteRes<[]>; 45 def Write_C : SchedWriteRes<[]>; 46 47 def : InstRW<[Write_A], (instrs Inst_A)>; 48 def : InstRW<[Write_B], (instrs Inst_B)>; 49 def : InstRW<[Write_C, Read_D], (instrs Inst_C)>; 50 51 def : ReadAdvance<Read_D, 1, [Write_B]>; 52} 53 54def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>; 55