xref: /llvm-project/llvm/test/TableGen/AsmWriterPCRelOp.td (revision 36111f28edb1182273c6409c3fb7808e0e9cbd60) 
1// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s
2
3include "llvm/Target/Target.td"
4
5def ArchInstrInfo : InstrInfo { }
6
7def Arch : Target {
8  let InstructionSet = ArchInstrInfo;
9}
10
11def R0 : Register<"r0">;
12def Reg : RegisterClass<"Reg", [i32], 0, (add R0)>;
13
14def IntOperand: Operand<i32>;
15
16def PCRelOperand : Operand<i32> {
17  let OperandType = "OPERAND_PCREL";
18}
19
20def foo : Instruction {
21  let OutOperandList = (outs);
22  let InOperandList = (ins Reg:$reg, IntOperand:$imm);
23  let AsmString = "foo $reg, $imm";
24}
25
26def bar : Instruction {
27  let OutOperandList = (outs);
28  let InOperandList = (ins Reg:$reg, PCRelOperand:$imm);
29  let AsmString = "bar $reg, $imm";
30}
31
32// CHECK:      ArchInstPrinter::printInstruction(
33// CHECK:      // bar, foo
34// CHECK-NEXT: printOperand(MI, 0, O);
35// CHECK:      // foo
36// CHECK-NEXT: printOperand(MI, 1, O);
37// CHECK:      // bar
38// CHECK-NEXT: printOperand(MI, Address, 1, O);
39