1// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | \ 2// RUN: FileCheck --check-prefix=DISASS %s 3// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | \ 4// RUN: FileCheck --check-prefix=MATCHER %s 5// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | \ 6// RUN: FileCheck --check-prefix=WRITER %s 7 8// Check that combining conditions in AssemblerPredicate generates the correct 9// output when using both the (all_of) AND operator, and the (any_of) OR 10// operator. 11 12include "llvm/Target/Target.td" 13 14def archInstrInfo : InstrInfo { } 15def archAsmWriter : AsmWriter { 16 int PassSubtarget = 1; 17} 18 19def arch : Target { 20 let InstructionSet = archInstrInfo; 21 let AssemblyWriters = [archAsmWriter]; 22} 23 24let Namespace = "arch" in { 25 def R0 : Register<"r0">; 26 def R1 : Register<"r1">; 27 def R2 : Register<"r2">; 28 def R3 : Register<"r3">; 29 def R4 : Register<"r4">; 30} 31def Regs : RegisterClass<"Regs", [i32], 32, (add R0, R1, R2, R3, R4)>; 32 33class TestInsn<int Opc, list<Predicate> Preds> : Instruction { 34 let Size = 2; 35 let OutOperandList = (outs); 36 let InOperandList = (ins Regs:$r); 37 field bits<16> Inst; 38 let Inst = Opc; 39 let AsmString = NAME # " $r"; 40 field bits<16> SoftFail = 0; 41 let Predicates = Preds; 42} 43 44 45def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">; 46def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">; 47def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">; 48def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">; 49def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">; 50def AsmCond4 : SubtargetFeature<"cond4", "cond4", "true", "">; 51 52def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>; 53def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>; 54def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>; 55def AsmPred4 : Predicate<"Pred4">, AssemblerPredicate<(all_of AsmCond4, (not (any_of AsmCond3a, AsmCond3b)))>; 56// MATCHER: if (FB[arch::AsmCond1]) 57// MATCHER-NEXT: Features.set(Feature_AsmPred1Bit); 58// MATCHER-NEXT: if (FB[arch::AsmCond2a] && FB[arch::AsmCond2b]) 59// MATCHER-NEXT: Features.set(Feature_AsmPred2Bit); 60// MATCHER-NEXT: if (FB[arch::AsmCond3a] || FB[arch::AsmCond3b]) 61// MATCHER-NEXT: Features.set(Feature_AsmPred3Bit); 62// MATCHER-NEXT: if (FB[arch::AsmCond4] && !(FB[arch::AsmCond3a] || FB[arch::AsmCond3b])) 63// MATCHER-NEXT: Features.set(Feature_AsmPred4Bit); 64 65def insn1 : TestInsn<1, [AsmPred1]>; 66// DISASS: return (Bits[arch::AsmCond1]); 67 68def insn2 : TestInsn<2, [AsmPred2]>; 69// DISASS: return (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b]) 70 71def insn3 : TestInsn<3, [AsmPred3]>; 72// DISASS: return (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b]) 73 74def insn4 : TestInsn<4, [AsmPred1, AsmPred2]>; 75// DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond2a] && Bits[arch::AsmCond2b])) 76 77def insn5 : TestInsn<5, [AsmPred1, AsmPred3]>; 78// DISASS: return (Bits[arch::AsmCond1] && (Bits[arch::AsmCond3a] || Bits[arch::AsmCond3b])) 79 80def insn6 : TestInsn<6, []>; 81def : InstAlias<"alias1", (insn6 R0)> { let Predicates = [AsmPred1]; } 82// WRITER: // (insn6 R0) 83// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R0}, 84// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1}, 85def : InstAlias<"alias2", (insn6 R1)> { let Predicates = [AsmPred2]; } 86// WRITER: // (insn6 R1) 87// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R1}, 88// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2a}, 89// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2b}, 90def : InstAlias<"alias3", (insn6 R2)> { let Predicates = [AsmPred3]; } 91// WRITER: // (insn6 R2) 92// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R2}, 93// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3a}, 94// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3b}, 95// WRITER-NEXT: {AliasPatternCond::K_EndOrFeatures, 0}, 96def : InstAlias<"alias4", (insn6 R3)> { let Predicates = [AsmPred1, AsmPred2]; } 97// WRITER: // (insn6 R3) 98// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R3}, 99// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1}, 100// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2a}, 101// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond2b}, 102def : InstAlias<"alias5", (insn6 R4)> { let Predicates = [AsmPred1, AsmPred3]; } 103// WRITER: // (insn6 R4) 104// WRITER-NEXT: {AliasPatternCond::K_Reg, arch::R4}, 105// WRITER-NEXT: {AliasPatternCond::K_Feature, arch::AsmCond1}, 106// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3a}, 107// WRITER-NEXT: {AliasPatternCond::K_OrFeature, arch::AsmCond3b}, 108// WRITER-NEXT: {AliasPatternCond::K_EndOrFeatures, 0}, 109