1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 2# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=none %s -o - | FileCheck %s 3 4# During the MachineVerifier, it assumes that used registers have been defined 5# In this test case, while $v12_v13_v14_v15_v16 covers $v14_v15, 6# $v14_v15 is not a sub-register of $v14m2 even though they share the same register. 7# This corner case can be resolved by checking the register using RegUnit. 8 9... 10--- 11name: func 12tracksRegLiveness: true 13tracksDebugUserValues: true 14body: | 15 bb.0: 16 liveins: $v0, $v8, $v9, $v10, $v11 17 18 ; CHECK-LABEL: name: func 19 ; CHECK: liveins: $v0, $v8, $v9, $v10, $v11 20 ; CHECK-NEXT: {{ $}} 21 ; CHECK-NEXT: renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype 22 ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16, implicit $vtype 23 renamable $v16m2 = PseudoVMV_V_I_M2 undef renamable $v16m2, 0, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype 24 $v20m2 = VMV2R_V $v14m2, implicit $v12_v13_v14_v15_v16, implicit $vtype 25 26... 27