xref: /llvm-project/llvm/test/MC/Xtensa/Core/processor-control.s (revision 4e0c1d98d3717d10e0230604a088ef38a3f7e060)
1# RUN: llvm-mc %s -triple=xtensa -show-encoding \
2# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
3
4
5.align	4
6LBL0:
7
8# Instruction format RRR
9# CHECK-INST: dsync
10# CHECK: encoding: [0x30,0x20,0x00]
11dsync
12
13# Instruction format RRR
14# CHECK-INST: esync
15# CHECK: encoding: [0x20,0x20,0x00]
16esync
17
18# Instruction format RRR
19# CHECK-INST: isync
20# CHECK: encoding: [0x00,0x20,0x00]
21isync
22
23# Instruction format RRR
24# CHECK-INST: nop
25# CHECK: encoding: [0xf0,0x20,0x00]
26nop
27
28# Instruction format RSR
29# CHECK-INST: rsr a8, sar
30# CHECK: encoding: [0x80,0x03,0x03]
31rsr a8, sar
32
33# CHECK-INST: rsr a8, sar
34# CHECK: encoding: [0x80,0x03,0x03]
35rsr.sar a8
36
37# CHECK-INST: rsr a8, sar
38# CHECK: encoding: [0x80,0x03,0x03]
39rsr a8, 3
40
41# Instruction format RRR
42# CHECK-INST: rsync
43# CHECK: encoding: [0x10,0x20,0x00]
44rsync
45
46# Instruction format RSR
47# CHECK-INST: wsr a8, sar
48# CHECK: encoding: [0x80,0x03,0x13]
49wsr a8, sar
50
51# CHECK-INST: wsr a8, sar
52# CHECK: encoding: [0x80,0x03,0x13]
53wsr.sar a8
54
55# CHECK-INST: wsr a8, sar
56# CHECK: encoding: [0x80,0x03,0x13]
57wsr a8, 3
58
59# Instruction format RRR
60# CHECK-INST: xsr a8, sar
61# CHECK: encoding: [0x80,0x03,0x61]
62xsr a8, sar
63
64# CHECK-INST: xsr a8, sar
65# CHECK: encoding: [0x80,0x03,0x61]
66xsr.sar a8
67
68# CHECK-INST: xsr a8, sar
69# CHECK: encoding: [0x80,0x03,0x61]
70xsr a8, 3
71