xref: /llvm-project/llvm/test/MC/RISCV/supervisor-csr-names.s (revision 4b3d439e7e7b4e794e523caea9863d67ff8cf85f) 
1# RUN: llvm-mc %s -triple=riscv32 -M no-aliases -show-encoding \
2# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
3# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
4# RUN:     | llvm-objdump -d - \
5# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
6#
7# RUN: llvm-mc %s -triple=riscv64 -M no-aliases -show-encoding \
8# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
9# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
10# RUN:     | llvm-objdump -d - \
11# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
12
13##################################
14# Supervisor Trap Setup
15##################################
16
17# sstatus
18# name
19# CHECK-INST: csrrs t1, sstatus, zero
20# CHECK-ENC: encoding: [0x73,0x23,0x00,0x10]
21# CHECK-INST-ALIAS: csrr t1, sstatus
22# uimm12
23# CHECK-INST: csrrs t2, sstatus, zero
24# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x10]
25# CHECK-INST-ALIAS: csrr t2, sstatus
26# name
27csrrs t1, sstatus, zero
28# uimm12
29csrrs t2, 0x100, zero
30
31# sie
32# name
33# CHECK-INST: csrrs t1, sie, zero
34# CHECK-ENC: [0x73,0x23,0x40,0x10]
35# CHECK-INST-ALIAS: csrr t1, sie
36# uimm12
37# CHECK-INST: csrrs t2, sie, zero
38# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x10]
39# CHECK-INST-ALIAS: csrr t2, sie
40# name
41csrrs t1, sie, zero
42# uimm12
43csrrs t2, 0x104, zero
44
45# stvec
46# name
47# CHECK-INST: csrrs t1, stvec, zero
48# CHECK-ENC: encoding: [0x73,0x23,0x50,0x10]
49# CHECK-INST-ALIAS: csrr t1, stvec
50# uimm12
51# CHECK-INST: csrrs t2, stvec, zero
52# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x10]
53# CHECK-INST-ALIAS: csrr t2, stvec
54# name
55csrrs t1, stvec, zero
56# uimm12
57csrrs t2, 0x105, zero
58
59# scounteren
60# name
61# CHECK-INST: csrrs t1, scounteren, zero
62# CHECK-ENC: encoding: [0x73,0x23,0x60,0x10]
63# CHECK-INST-ALIAS: csrr t1, scounteren
64# uimm12
65# CHECK-INST: csrrs t2, scounteren, zero
66# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x10]
67# CHECK-INST-ALIAS: csrr t2, scounteren
68# name
69csrrs t1, scounteren, zero
70# uimm12
71csrrs t2, 0x106, zero
72
73# stimecmp
74# name
75# CHECK-INST: csrrs t1, stimecmp, zero
76# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x14]
77# CHECK-INST-ALIAS: csrr t1, stimecmp
78# uimm12
79# CHECK-INST: csrrs t2, stimecmp, zero
80# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x14]
81# CHECK-INST-ALIAS: csrr t2, stimecmp
82# name
83csrrs t1, stimecmp, zero
84# uimm12
85csrrs t2, 0x14D, zero
86
87##################################
88# Supervisor Configuration
89##################################
90
91# senvcfg
92# name
93# CHECK-INST: csrrs t1, senvcfg, zero
94# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x10]
95# CHECK-INST-ALIAS: csrr t1, senvcfg
96# uimm12
97# CHECK-INST: csrrs t2, senvcfg, zero
98# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x10]
99# CHECK-INST-ALIAS: csrr t2, senvcfg
100# name
101csrrs t1, senvcfg, zero
102# uimm12
103csrrs t2, 0x10A, zero
104
105##################################
106# Supervisor Trap Handling
107##################################
108
109# sscratch
110# name
111# CHECK-INST: csrrs t1, sscratch, zero
112# CHECK-ENC: encoding: [0x73,0x23,0x00,0x14]
113# CHECK-INST-ALIAS: csrr t1, sscratch
114# uimm12
115# CHECK-INST: csrrs t2, sscratch, zero
116# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x14]
117# CHECK-INST-ALIAS: csrr t2, sscratch
118# name
119csrrs t1, sscratch, zero
120# uimm12
121csrrs t2, 0x140, zero
122
123# sepc
124# name
125# CHECK-INST: csrrs t1, sepc, zero
126# CHECK-ENC: encoding: [0x73,0x23,0x10,0x14]
127# CHECK-INST-ALIAS: csrr t1, sepc
128# uimm12
129# CHECK-INST: csrrs t2, sepc, zero
130# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x14]
131# CHECK-INST-ALIAS: csrr t2, sepc
132# name
133csrrs t1, sepc, zero
134# uimm12
135csrrs t2, 0x141, zero
136
137# scause
138# name
139# CHECK-INST: csrrs t1, scause, zero
140# CHECK-ENC: encoding: [0x73,0x23,0x20,0x14]
141# CHECK-INST-ALIAS: csrr t1, scause
142# uimm12
143# CHECK-INST: csrrs t2, scause, zero
144# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x14]
145# CHECK-INST-ALIAS: csrr t2, scause
146# name
147csrrs t1, scause, zero
148# uimm12
149csrrs t2, 0x142, zero
150
151# stval
152# name
153# CHECK-INST: csrrs t1, stval, zero
154# CHECK-ENC: encoding: [0x73,0x23,0x30,0x14]
155# CHECK-INST-ALIAS: csrr t1, stval
156# uimm12
157# CHECK-INST: csrrs t2, stval, zero
158# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x14]
159# CHECK-INST-ALIAS: csrr t2, stval
160# aliases
161# aliases with uimm12
162# name
163csrrs t1, stval, zero
164# uimm12
165csrrs t2, 0x143, zero
166
167# sip
168# name
169# CHECK-INST: csrrs t1, sip, zero
170# CHECK-ENC: encoding: [0x73,0x23,0x40,0x14]
171# CHECK-INST-ALIAS: csrr t1, sip
172# uimm12
173# CHECK-INST: csrrs t2, sip, zero
174# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x14]
175# CHECK-INST-ALIAS: csrr t2, sip
176csrrs t1, sip, zero
177# uimm12
178csrrs t2, 0x144, zero
179
180
181#########################################
182# Supervisor Protection and Translation
183#########################################
184
185# satp
186# name
187# CHECK-INST: csrrs t1, satp, zero
188# CHECK-ENC: encoding: [0x73,0x23,0x00,0x18]
189# CHECK-INST-ALIAS: csrr t1, satp
190# uimm12
191# CHECK-INST: csrrs t2, satp, zero
192# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x18]
193# CHECK-INST-ALIAS: csrr t2, satp
194# name
195csrrs t1, satp, zero
196# uimm12
197csrrs t2, 0x180, zero
198
199#########################################
200# Quality-of-Service(QoS) Identifiers
201#########################################
202
203# srmcfg
204# name
205# CHECK-INST: csrrs t1, srmcfg, zero
206# CHECK-ENC: encoding: [0x73,0x23,0x10,0x18]
207# CHECK-INST-ALIAS: csrr t1, srmcfg
208# uimm12
209# CHECK-INST: csrrs t2, srmcfg, zero
210# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x18]
211# CHECK-INST-ALIAS: csrr t2, srmcfg
212# name
213csrrs t1, srmcfg, zero
214# uimm12
215csrrs t2, 0x181, zero
216
217#########################################
218# Debug/Trace Registers
219#########################################
220
221# scontext
222# name
223# CHECK-INST: csrrs t1, scontext, zero
224# CHECK-ENC: encoding: [0x73,0x23,0x80,0x5a]
225# CHECK-INST-ALIAS: csrr t1, scontext
226# uimm12
227# CHECK-INST: csrrs t2, scontext, zero
228# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x5a]
229# CHECK-INST-ALIAS: csrr t2, scontext
230# name
231csrrs t1, scontext, zero
232# uimm12
233csrrs t2, 0x5A8, zero
234
235#########################################
236# Supervisor Count Overflow (Sscofpmf)
237#########################################
238
239# scountovf
240# name
241# CHECK-INST: csrrs t1, scountovf, zero
242# CHECK-ENC: encoding: [0x73,0x23,0x00,0xda]
243# CHECK-INST-ALIAS: csrr t1, scountovf
244# uimm12
245# CHECK-INST: csrrs t2, scountovf, zero
246# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xda]
247# CHECK-INST-ALIAS: csrr t2, scountovf
248# name
249csrrs t1, scountovf, zero
250# uimm12
251csrrs t2, 0xDA0, zero
252
253#########################################
254# State Enable Extension (Smstateen)
255#########################################
256
257# sstateen0
258# name
259# CHECK-INST: csrrs t1, sstateen0, zero
260# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x10]
261# CHECK-INST-ALIAS: csrr t1, sstateen0
262# uimm12
263# CHECK-INST: csrrs t2, sstateen0, zero
264# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x10]
265# CHECK-INST-ALIAS: csrr t2, sstateen0
266# name
267csrrs t1, sstateen0, zero
268# uimm12
269csrrs t2, 0x10C, zero
270
271# sstateen1
272# name
273# CHECK-INST: csrrs t1, sstateen1, zero
274# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x10]
275# CHECK-INST-ALIAS: csrr t1, sstateen1
276# uimm12
277# CHECK-INST: csrrs t2, sstateen1, zero
278# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x10]
279# CHECK-INST-ALIAS: csrr t2, sstateen1
280# name
281csrrs t1, sstateen1, zero
282# uimm12
283csrrs t2, 0x10D, zero
284
285# sstateen2
286# name
287# CHECK-INST: csrrs t1, sstateen2, zero
288# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x10]
289# CHECK-INST-ALIAS: csrr t1, sstateen2
290# uimm12
291# CHECK-INST: csrrs t2, sstateen2, zero
292# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x10]
293# CHECK-INST-ALIAS: csrr t2, sstateen2
294# name
295csrrs t1, sstateen2, zero
296# uimm12
297csrrs t2, 0x10E, zero
298
299# sstateen3
300# name
301# CHECK-INST: csrrs t1, sstateen3, zero
302# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x10]
303# CHECK-INST-ALIAS: csrr t1, sstateen3
304# uimm12
305# CHECK-INST: csrrs t2, sstateen3, zero
306# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x10]
307# CHECK-INST-ALIAS: csrr t2, sstateen3
308# name
309csrrs t1, sstateen3, zero
310# uimm12
311csrrs t2, 0x10F, zero
312
313#########################################
314# Advanced Interrupt Architecture (Smaia and Ssaia)
315#########################################
316
317# siselect
318# name
319# CHECK-INST: csrrs t1, siselect, zero
320# CHECK-ENC: encoding: [0x73,0x23,0x00,0x15]
321# CHECK-INST-ALIAS: csrr t1, siselect
322# uimm12
323# CHECK-INST: csrrs t2, siselect, zero
324# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x15]
325# CHECK-INST-ALIAS: csrr t2, siselect
326# name
327csrrs t1, siselect, zero
328# uimm12
329csrrs t2, 0x150, zero
330
331# sireg
332# name
333# CHECK-INST: csrrs t1, sireg, zero
334# CHECK-ENC: encoding: [0x73,0x23,0x10,0x15]
335# CHECK-INST-ALIAS: csrr t1, sireg
336# uimm12
337# CHECK-INST: csrrs t2, sireg, zero
338# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x15]
339# CHECK-INST-ALIAS: csrr t2, sireg
340# name
341csrrs t1, sireg, zero
342# uimm12
343csrrs t2, 0x151, zero
344
345# sireg2
346# name
347# CHECK-INST: csrrs t1, sireg2, zero
348# CHECK-ENC: encoding: [0x73,0x23,0x20,0x15]
349# CHECK-INST-ALIAS: csrr t1, sireg2
350# uimm12
351# CHECK-INST: csrrs t2, sireg2, zero
352# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x15]
353# CHECK-INST-ALIAS: csrr t2, sireg2
354# name
355csrrs t1, sireg2, zero
356# uimm12
357csrrs t2, 0x152, zero
358
359# sireg3
360# name
361# CHECK-INST: csrrs t1, sireg3, zero
362# CHECK-ENC: encoding: [0x73,0x23,0x30,0x15]
363# CHECK-INST-ALIAS: csrr t1, sireg3
364# uimm12
365# CHECK-INST: csrrs t2, sireg3, zero
366# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x15]
367# CHECK-INST-ALIAS: csrr t2, sireg3
368# name
369csrrs t1, sireg3, zero
370# uimm12
371csrrs t2, 0x153, zero
372
373# sireg4
374# name
375# CHECK-INST: csrrs t1, sireg4, zero
376# CHECK-ENC: encoding: [0x73,0x23,0x50,0x15]
377# CHECK-INST-ALIAS: csrr t1, sireg4
378# uimm12
379# CHECK-INST: csrrs t2, sireg4, zero
380# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x15]
381# CHECK-INST-ALIAS: csrr t2, sireg4
382# name
383csrrs t1, sireg4, zero
384# uimm12
385csrrs t2, 0x155, zero
386
387# sireg5
388# name
389# CHECK-INST: csrrs t1, sireg5, zero
390# CHECK-ENC: encoding: [0x73,0x23,0x60,0x15]
391# CHECK-INST-ALIAS: csrr t1, sireg5
392# uimm12
393# CHECK-INST: csrrs t2, sireg5, zero
394# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x15]
395# CHECK-INST-ALIAS: csrr t2, sireg5
396# name
397csrrs t1, sireg5, zero
398# uimm12
399csrrs t2, 0x156, zero
400
401# sireg6
402# name
403# CHECK-INST: csrrs t1, sireg6, zero
404# CHECK-ENC: encoding: [0x73,0x23,0x70,0x15]
405# CHECK-INST-ALIAS: csrr t1, sireg6
406# uimm12
407# CHECK-INST: csrrs t2, sireg6, zero
408# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x15]
409# CHECK-INST-ALIAS: csrr t2, sireg6
410# name
411csrrs t1, sireg6, zero
412# uimm12
413csrrs t2, 0x157, zero
414
415# stopei
416# name
417# CHECK-INST: csrrs t1, stopei, zero
418# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x15]
419# CHECK-INST-ALIAS: csrr t1, stopei
420# uimm12
421# CHECK-INST: csrrs t2, stopei, zero
422# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x15]
423# CHECK-INST-ALIAS: csrr t2, stopei
424# name
425csrrs t1, stopei, zero
426# uimm12
427csrrs t2, 0x15C, zero
428
429# stopi
430# name
431# CHECK-INST: csrrs t1, stopi, zero
432# CHECK-ENC: encoding: [0x73,0x23,0x00,0xdb]
433# CHECK-INST-ALIAS: csrr t1, stopi
434# uimm12
435# CHECK-INST: csrrs t2, stopi, zero
436# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xdb]
437# CHECK-INST-ALIAS: csrr t2, stopi
438# name
439csrrs t1, stopi, zero
440# uimm12
441csrrs t2, 0xDB0, zero
442
443#########################################
444# Counter Configuration (Ssccfg)
445#########################################
446
447# scountinhibit
448# name
449# CHECK-INST: csrrs t1, scountinhibit, zero
450# CHECK-ENC: encoding: [0x73,0x23,0x00,0x12]
451# CHECK-INST-ALIAS: csrr t1, scountinhibit
452# uimm12
453# CHECK-INST: csrrs t2, scountinhibit, zero
454# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x12]
455# CHECK-INST-ALIAS: csrr t2, scountinhibit
456# name
457csrrs t1, scountinhibit, zero
458# uimm12
459csrrs t2, 0x120, zero
460
461##################################
462# Control Transfer Records
463##################################
464
465# sctrctl
466# name
467# CHECK-INST: csrrs t1, sctrctl, zero
468# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x14]
469# CHECK-INST-ALIAS: csrr t1, sctrctl
470# uimm12
471# CHECK-INST: csrrs t2, sctrctl, zero
472# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x14]
473# CHECK-INST-ALIAS: csrr t2, sctrctl
474csrrs t1, sctrctl, zero
475# uimm12
476csrrs t2, 0x14E, zero
477
478# sctrstatus
479# name
480# CHECK-INST: csrrs t1, sctrstatus, zero
481# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x14]
482# CHECK-INST-ALIAS: csrr t1, sctrstatus
483# uimm12
484# CHECK-INST: csrrs t2, sctrstatus, zero
485# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x14]
486# CHECK-INST-ALIAS: csrr t2, sctrstatus
487csrrs t1, sctrstatus, zero
488# uimm12
489csrrs t2, 0x14F, zero
490
491# sctrdepth
492# name
493# CHECK-INST: csrrs t1, sctrdepth, zero
494# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x15]
495# CHECK-INST-ALIAS: csrr t1, sctrdepth
496# uimm12
497# CHECK-INST: csrrs t2, sctrdepth, zero
498# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x15]
499# CHECK-INST-ALIAS: csrr t2, sctrdepth
500csrrs t1, sctrdepth, zero
501# uimm12
502csrrs t2, 0x15F, zero
503