1# RUN: llvm-mc %s -triple=riscv32 -mattr=+f -M no-aliases \ 2# RUN: | FileCheck -check-prefix=CHECK-INST %s 3# RUN: llvm-mc %s -triple=riscv32 -mattr=+f \ 4# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s 5# RUN: llvm-mc %s -triple=riscv64 -mattr=+f -M no-aliases \ 6# RUN: | FileCheck -check-prefix=CHECK-INST %s 7# RUN: llvm-mc %s -triple=riscv64 -mattr=+f \ 8# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s 9# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ 10# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+f -M no-aliases - \ 11# RUN: | FileCheck -check-prefix=CHECK-INST %s 12# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ 13# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+f - \ 14# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s 15# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ 16# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+f -M no-aliases - \ 17# RUN: | FileCheck -check-prefix=CHECK-INST %s 18# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ 19# RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+f - \ 20# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s 21 22##===----------------------------------------------------------------------===## 23## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 24##===----------------------------------------------------------------------===## 25 26# CHECK-INST: flw ft0, 0(a0) 27# CHECK-ALIAS: flw ft0, 0(a0) 28flw f0, (a0) 29# CHECK-INST: fsw ft0, 0(a0) 30# CHECK-ALIAS: fsw ft0, 0(a0) 31fsw f0, (a0) 32 33# CHECK-INST: fsgnj.s ft0, ft1, ft1 34# CHECK-ALIAS: fmv.s ft0, ft1 35fmv.s f0, f1 36# CHECK-INST: fsgnjx.s ft1, ft2, ft2 37# CHECK-ALIAS: fabs.s ft1, ft2 38fabs.s f1, f2 39# CHECK-INST: fsgnjn.s ft2, ft3, ft3 40# CHECK-ALIAS: fneg.s ft2, ft3 41fneg.s f2, f3 42 43# CHECK-INST: flt.s tp, ft6, ft5 44# CHECK-ALIAS: flt.s tp, ft6, ft5 45fgt.s x4, f5, f6 46# CHECK-INST: fle.s t2, fs1, fs0 47# CHECK-ALIAS: fle.s t2, fs1, fs0 48fge.s x7, f8, f9 49 50# The following instructions actually alias instructions from the base ISA. 51# However, it only makes sense to support them when the F or Zfinx extension is 52# enabled. 53# CHECK-INST: csrrs t0, fcsr, zero 54# CHECK-ALIAS: frcsr t0 55frcsr x5 56# CHECK-INST: csrrw t1, fcsr, t2 57# CHECK-ALIAS: fscsr t1, t2 58fscsr x6, x7 59# CHECK-INST: csrrw zero, fcsr, t3 60# CHECK-ALIAS: fscsr t3 61fscsr x28 62 63# These are obsolete aliases of frcsr/fscsr. They are accepted by the assembler 64# but the disassembler should always print them as the equivalent, new aliases. 65# CHECK-INST: csrrs t4, fcsr, zero 66# CHECK-ALIAS: frcsr t4 67frsr x29 68# CHECK-INST: csrrw t5, fcsr, t6 69# CHECK-ALIAS: fscsr t5, t6 70fssr x30, x31 71# CHECK-INST: csrrw zero, fcsr, s0 72# CHECK-ALIAS: fscsr s0 73fssr x8 74 75# CHECK-INST: csrrs t4, frm, zero 76# CHECK-ALIAS: frrm t4 77frrm x29 78# CHECK-INST: csrrw t5, frm, t4 79# CHECK-ALIAS: fsrm t5, t4 80fsrm x30, x29 81# CHECK-INST: csrrw zero, frm, t6 82# CHECK-ALIAS: fsrm t6 83fsrm x31 84# CHECK-INST: csrrwi a0, frm, 31 85# CHECK-ALIAS: fsrmi a0, 31 86fsrmi x10, 0x1f 87# CHECK-INST: csrrwi zero, frm, 30 88# CHECK-ALIAS: fsrmi 30 89fsrmi 0x1e 90 91# CHECK-INST: csrrs a1, fflags, zero 92# CHECK-ALIAS: frflags a1 93frflags x11 94# CHECK-INST: csrrw a2, fflags, a1 95# CHECK-ALIAS: fsflags a2, a1 96fsflags x12, x11 97# CHECK-INST: csrrw zero, fflags, a3 98# CHECK-ALIAS: fsflags a3 99fsflags x13 100# CHECK-INST: csrrwi a4, fflags, 29 101# CHECK-ALIAS: fsflagsi a4, 29 102fsflagsi x14, 0x1d 103# CHECK-INST: csrrwi zero, fflags, 28 104# CHECK-ALIAS: fsflagsi 28 105fsflagsi 0x1c 106 107# CHECK-INST: fmv.x.w a2, fs7 108# CHECK-ALIAS: fmv.x.w a2, fs7 109fmv.x.s a2, fs7 110# CHECK-INST: fmv.w.x ft1, a6 111# CHECK-ALIAS: fmv.w.x ft1, a6 112fmv.s.x ft1, a6 113 114# CHECK-INST: flw ft0, 0(a0) 115# CHECK-ALIAS: flw ft0, 0(a0) 116flw f0, (x10) 117# CHECK-INST: fsw ft0, 0(a0) 118# CHECK-ALIAS: fsw ft0, 0(a0) 119fsw f0, (x10) 120 121##===----------------------------------------------------------------------===## 122## Aliases which omit the rounding mode. 123##===----------------------------------------------------------------------===## 124 125# CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, dyn 126# CHECK-ALIAS: fmadd.s fa0, fa1, fa2, fa3{{[[:space:]]}} 127fmadd.s f10, f11, f12, f13 128# CHECK-INST: fmsub.s fa4, fa5, fa6, fa7, dyn 129# CHECK-ALIAS: fmsub.s fa4, fa5, fa6, fa7{{[[:space:]]}} 130fmsub.s f14, f15, f16, f17 131# CHECK-INST: fnmsub.s fs2, fs3, fs4, fs5, dyn 132# CHECK-ALIAS: fnmsub.s fs2, fs3, fs4, fs5{{[[:space:]]}} 133fnmsub.s f18, f19, f20, f21 134# CHECK-INST: fnmadd.s fs6, fs7, fs8, fs9, dyn 135# CHECK-ALIAS: fnmadd.s fs6, fs7, fs8, fs9{{[[:space:]]}} 136fnmadd.s f22, f23, f24, f25 137# CHECK-INST: fadd.s fs10, fs11, ft8, dyn 138# CHECK-ALIAS: fadd.s fs10, fs11, ft8{{[[:space:]]}} 139fadd.s f26, f27, f28 140# CHECK-INST: fsub.s ft9, ft10, ft11, dyn 141# CHECK-ALIAS: fsub.s ft9, ft10, ft11{{[[:space:]]}} 142fsub.s f29, f30, f31 143# CHECK-INST: fmul.s ft0, ft1, ft2, dyn 144# CHECK-ALIAS: fmul.s ft0, ft1, ft2{{[[:space:]]}} 145fmul.s ft0, ft1, ft2 146# CHECK-INST: fdiv.s ft3, ft4, ft5, dyn 147# CHECK-ALIAS: fdiv.s ft3, ft4, ft5{{[[:space:]]}} 148fdiv.s ft3, ft4, ft5 149# CHECK-INST: fsqrt.s ft6, ft7, dyn 150# CHECK-ALIAS: fsqrt.s ft6, ft7{{[[:space:]]}} 151fsqrt.s ft6, ft7 152# CHECK-INST: fcvt.w.s a0, fs5, dyn 153# CHECK-ALIAS: fcvt.w.s a0, fs5{{[[:space:]]}} 154fcvt.w.s a0, fs5 155# CHECK-INST: fcvt.wu.s a1, fs6, dyn 156# CHECK-ALIAS: fcvt.wu.s a1, fs6{{[[:space:]]}} 157fcvt.wu.s a1, fs6 158# CHECK-INST: fcvt.s.w ft11, a4, dyn 159# CHECK-ALIAS: fcvt.s.w ft11, a4{{[[:space:]]}} 160fcvt.s.w ft11, a4 161# CHECK-INST: fcvt.s.wu ft0, a5, dyn 162# CHECK-ALIAS: fcvt.s.wu ft0, a5{{[[:space:]]}} 163fcvt.s.wu ft0, a5 164