xref: /llvm-project/llvm/test/MC/RISCV/rvd-aliases-valid.s (revision 4b3d439e7e7b4e794e523caea9863d67ff8cf85f)
1# RUN: llvm-mc %s -triple=riscv32 -mattr=+d -M no-aliases \
2# RUN:     | FileCheck -check-prefix=CHECK-INST %s
3# RUN: llvm-mc %s -triple=riscv32 -mattr=+d \
4# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
5# RUN: llvm-mc %s -triple=riscv64 -mattr=+d -M no-aliases \
6# RUN:     | FileCheck -check-prefix=CHECK-INST %s
7# RUN: llvm-mc %s -triple=riscv64 -mattr=+d \
8# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
9# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+d < %s \
10# RUN:     | llvm-objdump -d --mattr=+d --no-print-imm-hex -M no-aliases - \
11# RUN:     | FileCheck -check-prefix=CHECK-INST %s
12# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+d < %s \
13# RUN:     | llvm-objdump -d --mattr=+d --no-print-imm-hex - \
14# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
15# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+d < %s \
16# RUN:     | llvm-objdump -d --mattr=+d --no-print-imm-hex -M no-aliases - \
17# RUN:     | FileCheck -check-prefix=CHECK-INST %s
18# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+d < %s \
19# RUN:     | llvm-objdump -d --mattr=+d --no-print-imm-hex - \
20# RUN:     | FileCheck -check-prefix=CHECK-ALIAS %s
21
22##===----------------------------------------------------------------------===##
23## Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
24##===----------------------------------------------------------------------===##
25
26# CHECK-INST: fld ft0, 0(a0)
27# CHECK-ALIAS:  fld ft0, 0(a0)
28fld f0, (a0)
29# CHECK-INST: fsd ft0, 0(a0)
30# CHECK-ALIAS: fsd ft0, 0(a0)
31fsd f0, (a0)
32
33# CHECK-INST: fsgnj.d ft0, ft1, ft1
34# CHECK-ALIAS: fmv.d ft0, ft1
35fmv.d f0, f1
36# CHECK-INST: fsgnjx.d ft1, ft2, ft2
37# CHECK-ALIAS: fabs.d ft1, ft2
38fabs.d f1, f2
39# CHECK-INST: fsgnjn.d ft2, ft3, ft3
40# CHECK-ALIAS: fneg.d ft2, ft3
41fneg.d f2, f3
42
43# CHECK-INST: flt.d tp, ft6, ft5
44# CHECK-ALIAS: flt.d tp, ft6, ft5
45fgt.d x4, f5, f6
46# CHECK-INST: fle.d t2, fs1, fs0
47# CHECK-ALIAS: fle.d t2, fs1, fs0
48fge.d x7, f8, f9
49
50# CHECK-INST: fld ft0, 0(a0)
51# CHECK-ALIAS: fld ft0, 0(a0)
52fld f0, (x10)
53# CHECK-INST: fsd ft0, 0(a0)
54# CHECK-ALIAS: fsd ft0, 0(a0)
55fsd f0, (x10)
56
57##===----------------------------------------------------------------------===##
58## Aliases which omit the rounding mode.
59##===----------------------------------------------------------------------===##
60
61# CHECK-INST: fmadd.d fa0, fa1, fa2, fa3, dyn
62# CHECK-ALIAS: fmadd.d fa0, fa1, fa2, fa3{{[[:space:]]}}
63fmadd.d f10, f11, f12, f13
64# CHECK-INST: fmsub.d fa4, fa5, fa6, fa7, dyn
65# CHECK-ALIAS: fmsub.d fa4, fa5, fa6, fa7{{[[:space:]]}}
66fmsub.d f14, f15, f16, f17
67# CHECK-INST: fnmsub.d fs2, fs3, fs4, fs5, dyn
68# CHECK-ALIAS: fnmsub.d fs2, fs3, fs4, fs5{{[[:space:]]}}
69fnmsub.d f18, f19, f20, f21
70# CHECK-INST: fnmadd.d fs6, fs7, fs8, fs9, dyn
71# CHECK-ALIAS: fnmadd.d fs6, fs7, fs8, fs9{{[[:space:]]}}
72fnmadd.d f22, f23, f24, f25
73# CHECK-INST: fadd.d fs10, fs11, ft8, dyn
74# CHECK-ALIAS: fadd.d fs10, fs11, ft8{{[[:space:]]}}
75fadd.d f26, f27, f28
76# CHECK-INST: fsub.d ft9, ft10, ft11, dyn
77# CHECK-ALIAS: fsub.d ft9, ft10, ft11{{[[:space:]]}}
78fsub.d f29, f30, f31
79# CHECK-INST: fmul.d ft0, ft1, ft2, dyn
80# CHECK-ALIAS: fmul.d ft0, ft1, ft2{{[[:space:]]}}
81fmul.d ft0, ft1, ft2
82# CHECK-INST: fdiv.d ft3, ft4, ft5, dyn
83# CHECK-ALIAS: fdiv.d ft3, ft4, ft5{{[[:space:]]}}
84fdiv.d ft3, ft4, ft5
85# CHECK-INST: fsqrt.d ft6, ft7, dyn
86# CHECK-ALIAS: fsqrt.d ft6, ft7{{[[:space:]]}}
87fsqrt.d ft6, ft7
88# CHECK-INST: fcvt.s.d fs5, fs6, dyn
89# CHECK-ALIAS: fcvt.s.d fs5, fs6{{[[:space:]]}}
90fcvt.s.d fs5, fs6
91# CHECK-INST: fcvt.w.d a4, ft11, dyn
92# CHECK-ALIAS: fcvt.w.d a4, ft11{{[[:space:]]}}
93fcvt.w.d a4, ft11
94# CHECK-INST: fcvt.wu.d a5, ft10, dyn
95# CHECK-ALIAS: fcvt.wu.d a5, ft10{{[[:space:]]}}
96fcvt.wu.d a5, ft10
97