xref: /llvm-project/llvm/test/MC/RISCV/rv64zhinx-invalid.s (revision e56bf133170c9fd49c91fe943ded26a3f2b30a04)
1# RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s
2
3# Not support float registers
4flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
5
6# Invalid instructions
7fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
8fmv.x.h t2, a2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
9fmv.h.x a5, t5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
10
11# FP registers where integer regs are expected
12fcvt.h.l a2, ft2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
13fcvt.h.lu a3, ft3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
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