xref: /llvm-project/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s (revision eec05bfeafe9389e190932e0efbfbed11198311e)
1# RUN: not llvm-mc -triple riscv32 -mattr=+zhinxmin %s 2>&1 | FileCheck %s
2
3# Not support float registers
4flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
5fcvt.h.s fa0, fa1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
6
7# Invalid instructions
8fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
9fmv.x.h s0, s1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
10
11# Invalid register names
12fcvt.h.s a100, a1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
13
14# Valid in Zhinx
15fmadd.h x10, x11, x12, x13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer){{$}}
16