1# RUN: llvm-mc -triple=riscv32 --mattr=+xcvsimd -show-encoding %s \ 2# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR 3# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvsimd < %s \ 4# RUN: | llvm-objdump --mattr=+xcvsimd --no-print-imm-hex -M no-aliases -d -r - \ 5# RUN: | FileCheck --check-prefix=CHECK-INSTR %s 6# RUN: not llvm-mc -triple riscv32 %s 2>&1 \ 7# RUN: | FileCheck -check-prefix=CHECK-NO-EXT %s 8 9//===----------------------------------------------------------------------===// 10// cv.add.h 11//===----------------------------------------------------------------------===// 12 13cv.add.h t0, t1, t2 14# CHECK-INSTR: cv.add.h t0, t1, t2 15# CHECK-ENCODING: [0xfb,0x02,0x73,0x00] 16# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 17 18cv.add.h t3, t4, t5 19# CHECK-INSTR: cv.add.h t3, t4, t5 20# CHECK-ENCODING: [0x7b,0x8e,0xee,0x01] 21# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 22 23cv.add.h a0, a1, a2 24# CHECK-INSTR: cv.add.h a0, a1, a2 25# CHECK-ENCODING: [0x7b,0x85,0xc5,0x00] 26# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 27 28cv.add.h s0, s1, s2 29# CHECK-INSTR: cv.add.h s0, s1, s2 30# CHECK-ENCODING: [0x7b,0x84,0x24,0x01] 31# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 32 33//===----------------------------------------------------------------------===// 34// cv.add.b 35//===----------------------------------------------------------------------===// 36 37cv.add.b t0, t1, t2 38# CHECK-INSTR: cv.add.b t0, t1, t2 39# CHECK-ENCODING: [0xfb,0x12,0x73,0x00] 40# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 41 42cv.add.b t3, t4, t5 43# CHECK-INSTR: cv.add.b t3, t4, t5 44# CHECK-ENCODING: [0x7b,0x9e,0xee,0x01] 45# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 46 47cv.add.b a0, a1, a2 48# CHECK-INSTR: cv.add.b a0, a1, a2 49# CHECK-ENCODING: [0x7b,0x95,0xc5,0x00] 50# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 51 52cv.add.b s0, s1, s2 53# CHECK-INSTR: cv.add.b s0, s1, s2 54# CHECK-ENCODING: [0x7b,0x94,0x24,0x01] 55# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 56 57//===----------------------------------------------------------------------===// 58// cv.add.sc.h 59//===----------------------------------------------------------------------===// 60 61cv.add.sc.h t0, t1, t2 62# CHECK-INSTR: cv.add.sc.h t0, t1, t2 63# CHECK-ENCODING: [0xfb,0x42,0x73,0x00] 64# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 65 66cv.add.sc.h t3, t4, t5 67# CHECK-INSTR: cv.add.sc.h t3, t4, t5 68# CHECK-ENCODING: [0x7b,0xce,0xee,0x01] 69# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 70 71cv.add.sc.h a0, a1, a2 72# CHECK-INSTR: cv.add.sc.h a0, a1, a2 73# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x00] 74# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 75 76cv.add.sc.h s0, s1, s2 77# CHECK-INSTR: cv.add.sc.h s0, s1, s2 78# CHECK-ENCODING: [0x7b,0xc4,0x24,0x01] 79# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 80 81//===----------------------------------------------------------------------===// 82// cv.add.sc.b 83//===----------------------------------------------------------------------===// 84 85cv.add.sc.b t0, t1, t2 86# CHECK-INSTR: cv.add.sc.b t0, t1, t2 87# CHECK-ENCODING: [0xfb,0x52,0x73,0x00] 88# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 89 90cv.add.sc.b t3, t4, t5 91# CHECK-INSTR: cv.add.sc.b t3, t4, t5 92# CHECK-ENCODING: [0x7b,0xde,0xee,0x01] 93# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 94 95cv.add.sc.b a0, a1, a2 96# CHECK-INSTR: cv.add.sc.b a0, a1, a2 97# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x00] 98# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 99 100cv.add.sc.b s0, s1, s2 101# CHECK-INSTR: cv.add.sc.b s0, s1, s2 102# CHECK-ENCODING: [0x7b,0xd4,0x24,0x01] 103# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 104 105//===----------------------------------------------------------------------===// 106// cv.add.sci.h 107//===----------------------------------------------------------------------===// 108 109cv.add.sci.h t0, t1, 0 110# CHECK-INSTR: cv.add.sci.h t0, t1, 0 111# CHECK-ENCODING: [0xfb,0x62,0x03,0x00] 112# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 113 114cv.add.sci.h t3, t4, -32 115# CHECK-INSTR: cv.add.sci.h t3, t4, -32 116# CHECK-ENCODING: [0x7b,0xee,0x0e,0x01] 117# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 118 119cv.add.sci.h a0, a1, 7 120# CHECK-INSTR: cv.add.sci.h a0, a1, 7 121# CHECK-ENCODING: [0x7b,0xe5,0x35,0x02] 122# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 123 124cv.add.sci.h s0, s1, -1 125# CHECK-INSTR: cv.add.sci.h s0, s1, -1 126# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x03] 127# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 128 129//===----------------------------------------------------------------------===// 130// cv.add.sci.b 131//===----------------------------------------------------------------------===// 132 133cv.add.sci.b t0, t1, 0 134# CHECK-INSTR: cv.add.sci.b t0, t1, 0 135# CHECK-ENCODING: [0xfb,0x72,0x03,0x00] 136# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 137 138cv.add.sci.b t3, t4, -32 139# CHECK-INSTR: cv.add.sci.b t3, t4, -32 140# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x01] 141# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 142 143cv.add.sci.b a0, a1, 7 144# CHECK-INSTR: cv.add.sci.b a0, a1, 7 145# CHECK-ENCODING: [0x7b,0xf5,0x35,0x02] 146# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 147 148cv.add.sci.b s0, s1, -1 149# CHECK-INSTR: cv.add.sci.b s0, s1, -1 150# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x03] 151# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 152 153//===----------------------------------------------------------------------===// 154// cv.sub.h 155//===----------------------------------------------------------------------===// 156 157cv.sub.h t0, t1, t2 158# CHECK-INSTR: cv.sub.h t0, t1, t2 159# CHECK-ENCODING: [0xfb,0x02,0x73,0x08] 160# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 161 162cv.sub.h t3, t4, t5 163# CHECK-INSTR: cv.sub.h t3, t4, t5 164# CHECK-ENCODING: [0x7b,0x8e,0xee,0x09] 165# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 166 167cv.sub.h a0, a1, a2 168# CHECK-INSTR: cv.sub.h a0, a1, a2 169# CHECK-ENCODING: [0x7b,0x85,0xc5,0x08] 170# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 171 172cv.sub.h s0, s1, s2 173# CHECK-INSTR: cv.sub.h s0, s1, s2 174# CHECK-ENCODING: [0x7b,0x84,0x24,0x09] 175# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 176 177//===----------------------------------------------------------------------===// 178// cv.sub.b 179//===----------------------------------------------------------------------===// 180 181cv.sub.b t0, t1, t2 182# CHECK-INSTR: cv.sub.b t0, t1, t2 183# CHECK-ENCODING: [0xfb,0x12,0x73,0x08] 184# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 185 186cv.sub.b t3, t4, t5 187# CHECK-INSTR: cv.sub.b t3, t4, t5 188# CHECK-ENCODING: [0x7b,0x9e,0xee,0x09] 189# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 190 191cv.sub.b a0, a1, a2 192# CHECK-INSTR: cv.sub.b a0, a1, a2 193# CHECK-ENCODING: [0x7b,0x95,0xc5,0x08] 194# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 195 196cv.sub.b s0, s1, s2 197# CHECK-INSTR: cv.sub.b s0, s1, s2 198# CHECK-ENCODING: [0x7b,0x94,0x24,0x09] 199# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 200 201//===----------------------------------------------------------------------===// 202// cv.sub.sc.h 203//===----------------------------------------------------------------------===// 204 205cv.sub.sc.h t0, t1, t2 206# CHECK-INSTR: cv.sub.sc.h t0, t1, t2 207# CHECK-ENCODING: [0xfb,0x42,0x73,0x08] 208# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 209 210cv.sub.sc.h t3, t4, t5 211# CHECK-INSTR: cv.sub.sc.h t3, t4, t5 212# CHECK-ENCODING: [0x7b,0xce,0xee,0x09] 213# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 214 215cv.sub.sc.h a0, a1, a2 216# CHECK-INSTR: cv.sub.sc.h a0, a1, a2 217# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x08] 218# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 219 220cv.sub.sc.h s0, s1, s2 221# CHECK-INSTR: cv.sub.sc.h s0, s1, s2 222# CHECK-ENCODING: [0x7b,0xc4,0x24,0x09] 223# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 224 225//===----------------------------------------------------------------------===// 226// cv.sub.sc.b 227//===----------------------------------------------------------------------===// 228 229cv.sub.sc.b t0, t1, t2 230# CHECK-INSTR: cv.sub.sc.b t0, t1, t2 231# CHECK-ENCODING: [0xfb,0x52,0x73,0x08] 232# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 233 234cv.sub.sc.b t3, t4, t5 235# CHECK-INSTR: cv.sub.sc.b t3, t4, t5 236# CHECK-ENCODING: [0x7b,0xde,0xee,0x09] 237# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 238 239cv.sub.sc.b a0, a1, a2 240# CHECK-INSTR: cv.sub.sc.b a0, a1, a2 241# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x08] 242# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 243 244cv.sub.sc.b s0, s1, s2 245# CHECK-INSTR: cv.sub.sc.b s0, s1, s2 246# CHECK-ENCODING: [0x7b,0xd4,0x24,0x09] 247# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 248 249//===----------------------------------------------------------------------===// 250// cv.sub.sci.h 251//===----------------------------------------------------------------------===// 252 253cv.sub.sci.h t0, t1, 0 254# CHECK-INSTR: cv.sub.sci.h t0, t1, 0 255# CHECK-ENCODING: [0xfb,0x62,0x03,0x08] 256# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 257 258cv.sub.sci.h t3, t4, -32 259# CHECK-INSTR: cv.sub.sci.h t3, t4, -32 260# CHECK-ENCODING: [0x7b,0xee,0x0e,0x09] 261# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 262 263cv.sub.sci.h a0, a1, 7 264# CHECK-INSTR: cv.sub.sci.h a0, a1, 7 265# CHECK-ENCODING: [0x7b,0xe5,0x35,0x0a] 266# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 267 268cv.sub.sci.h s0, s1, -1 269# CHECK-INSTR: cv.sub.sci.h s0, s1, -1 270# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x0b] 271# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 272 273//===----------------------------------------------------------------------===// 274// cv.sub.sci.b 275//===----------------------------------------------------------------------===// 276 277cv.sub.sci.b t0, t1, 0 278# CHECK-INSTR: cv.sub.sci.b t0, t1, 0 279# CHECK-ENCODING: [0xfb,0x72,0x03,0x08] 280# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 281 282cv.sub.sci.b t3, t4, -32 283# CHECK-INSTR: cv.sub.sci.b t3, t4, -32 284# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x09] 285# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 286 287cv.sub.sci.b a0, a1, 7 288# CHECK-INSTR: cv.sub.sci.b a0, a1, 7 289# CHECK-ENCODING: [0x7b,0xf5,0x35,0x0a] 290# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 291 292cv.sub.sci.b s0, s1, -1 293# CHECK-INSTR: cv.sub.sci.b s0, s1, -1 294# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x0b] 295# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 296 297//===----------------------------------------------------------------------===// 298// cv.avg.h 299//===----------------------------------------------------------------------===// 300 301cv.avg.h t0, t1, t2 302# CHECK-INSTR: cv.avg.h t0, t1, t2 303# CHECK-ENCODING: [0xfb,0x02,0x73,0x10] 304# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 305 306cv.avg.h t3, t4, t5 307# CHECK-INSTR: cv.avg.h t3, t4, t5 308# CHECK-ENCODING: [0x7b,0x8e,0xee,0x11] 309# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 310 311cv.avg.h a0, a1, a2 312# CHECK-INSTR: cv.avg.h a0, a1, a2 313# CHECK-ENCODING: [0x7b,0x85,0xc5,0x10] 314# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 315 316cv.avg.h s0, s1, s2 317# CHECK-INSTR: cv.avg.h s0, s1, s2 318# CHECK-ENCODING: [0x7b,0x84,0x24,0x11] 319# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 320 321//===----------------------------------------------------------------------===// 322// cv.avg.b 323//===----------------------------------------------------------------------===// 324 325cv.avg.b t0, t1, t2 326# CHECK-INSTR: cv.avg.b t0, t1, t2 327# CHECK-ENCODING: [0xfb,0x12,0x73,0x10] 328# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 329 330cv.avg.b t3, t4, t5 331# CHECK-INSTR: cv.avg.b t3, t4, t5 332# CHECK-ENCODING: [0x7b,0x9e,0xee,0x11] 333# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 334 335cv.avg.b a0, a1, a2 336# CHECK-INSTR: cv.avg.b a0, a1, a2 337# CHECK-ENCODING: [0x7b,0x95,0xc5,0x10] 338# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 339 340cv.avg.b s0, s1, s2 341# CHECK-INSTR: cv.avg.b s0, s1, s2 342# CHECK-ENCODING: [0x7b,0x94,0x24,0x11] 343# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 344 345//===----------------------------------------------------------------------===// 346// cv.avg.sc.h 347//===----------------------------------------------------------------------===// 348 349cv.avg.sc.h t0, t1, t2 350# CHECK-INSTR: cv.avg.sc.h t0, t1, t2 351# CHECK-ENCODING: [0xfb,0x42,0x73,0x10] 352# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 353 354cv.avg.sc.h t3, t4, t5 355# CHECK-INSTR: cv.avg.sc.h t3, t4, t5 356# CHECK-ENCODING: [0x7b,0xce,0xee,0x11] 357# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 358 359cv.avg.sc.h a0, a1, a2 360# CHECK-INSTR: cv.avg.sc.h a0, a1, a2 361# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x10] 362# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 363 364cv.avg.sc.h s0, s1, s2 365# CHECK-INSTR: cv.avg.sc.h s0, s1, s2 366# CHECK-ENCODING: [0x7b,0xc4,0x24,0x11] 367# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 368 369//===----------------------------------------------------------------------===// 370// cv.avg.sc.b 371//===----------------------------------------------------------------------===// 372 373cv.avg.sc.b t0, t1, t2 374# CHECK-INSTR: cv.avg.sc.b t0, t1, t2 375# CHECK-ENCODING: [0xfb,0x52,0x73,0x10] 376# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 377 378cv.avg.sc.b t3, t4, t5 379# CHECK-INSTR: cv.avg.sc.b t3, t4, t5 380# CHECK-ENCODING: [0x7b,0xde,0xee,0x11] 381# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 382 383cv.avg.sc.b a0, a1, a2 384# CHECK-INSTR: cv.avg.sc.b a0, a1, a2 385# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x10] 386# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 387 388cv.avg.sc.b s0, s1, s2 389# CHECK-INSTR: cv.avg.sc.b s0, s1, s2 390# CHECK-ENCODING: [0x7b,0xd4,0x24,0x11] 391# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 392 393//===----------------------------------------------------------------------===// 394// cv.avg.sci.h 395//===----------------------------------------------------------------------===// 396 397cv.avg.sci.h t0, t1, 0 398# CHECK-INSTR: cv.avg.sci.h t0, t1, 0 399# CHECK-ENCODING: [0xfb,0x62,0x03,0x10] 400# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 401 402cv.avg.sci.h t3, t4, -32 403# CHECK-INSTR: cv.avg.sci.h t3, t4, -32 404# CHECK-ENCODING: [0x7b,0xee,0x0e,0x11] 405# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 406 407cv.avg.sci.h a0, a1, 7 408# CHECK-INSTR: cv.avg.sci.h a0, a1, 7 409# CHECK-ENCODING: [0x7b,0xe5,0x35,0x12] 410# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 411 412cv.avg.sci.h s0, s1, -1 413# CHECK-INSTR: cv.avg.sci.h s0, s1, -1 414# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x13] 415# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 416 417//===----------------------------------------------------------------------===// 418// cv.avg.sci.b 419//===----------------------------------------------------------------------===// 420 421cv.avg.sci.b t0, t1, 0 422# CHECK-INSTR: cv.avg.sci.b t0, t1, 0 423# CHECK-ENCODING: [0xfb,0x72,0x03,0x10] 424# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 425 426cv.avg.sci.b t3, t4, -32 427# CHECK-INSTR: cv.avg.sci.b t3, t4, -32 428# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x11] 429# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 430 431cv.avg.sci.b a0, a1, 7 432# CHECK-INSTR: cv.avg.sci.b a0, a1, 7 433# CHECK-ENCODING: [0x7b,0xf5,0x35,0x12] 434# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 435 436cv.avg.sci.b s0, s1, -1 437# CHECK-INSTR: cv.avg.sci.b s0, s1, -1 438# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x13] 439# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 440 441//===----------------------------------------------------------------------===// 442// cv.avgu.h 443//===----------------------------------------------------------------------===// 444 445cv.avgu.h t0, t1, t2 446# CHECK-INSTR: cv.avgu.h t0, t1, t2 447# CHECK-ENCODING: [0xfb,0x02,0x73,0x18] 448# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 449 450cv.avgu.h t3, t4, t5 451# CHECK-INSTR: cv.avgu.h t3, t4, t5 452# CHECK-ENCODING: [0x7b,0x8e,0xee,0x19] 453# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 454 455cv.avgu.h a0, a1, a2 456# CHECK-INSTR: cv.avgu.h a0, a1, a2 457# CHECK-ENCODING: [0x7b,0x85,0xc5,0x18] 458# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 459 460cv.avgu.h s0, s1, s2 461# CHECK-INSTR: cv.avgu.h s0, s1, s2 462# CHECK-ENCODING: [0x7b,0x84,0x24,0x19] 463# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 464 465//===----------------------------------------------------------------------===// 466// cv.avgu.b 467//===----------------------------------------------------------------------===// 468 469cv.avgu.b t0, t1, t2 470# CHECK-INSTR: cv.avgu.b t0, t1, t2 471# CHECK-ENCODING: [0xfb,0x12,0x73,0x18] 472# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 473 474cv.avgu.b t3, t4, t5 475# CHECK-INSTR: cv.avgu.b t3, t4, t5 476# CHECK-ENCODING: [0x7b,0x9e,0xee,0x19] 477# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 478 479cv.avgu.b a0, a1, a2 480# CHECK-INSTR: cv.avgu.b a0, a1, a2 481# CHECK-ENCODING: [0x7b,0x95,0xc5,0x18] 482# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 483 484cv.avgu.b s0, s1, s2 485# CHECK-INSTR: cv.avgu.b s0, s1, s2 486# CHECK-ENCODING: [0x7b,0x94,0x24,0x19] 487# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 488 489//===----------------------------------------------------------------------===// 490// cv.avgu.sc.h 491//===----------------------------------------------------------------------===// 492 493cv.avgu.sc.h t0, t1, t2 494# CHECK-INSTR: cv.avgu.sc.h t0, t1, t2 495# CHECK-ENCODING: [0xfb,0x42,0x73,0x18] 496# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 497 498cv.avgu.sc.h t3, t4, t5 499# CHECK-INSTR: cv.avgu.sc.h t3, t4, t5 500# CHECK-ENCODING: [0x7b,0xce,0xee,0x19] 501# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 502 503cv.avgu.sc.h a0, a1, a2 504# CHECK-INSTR: cv.avgu.sc.h a0, a1, a2 505# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x18] 506# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 507 508cv.avgu.sc.h s0, s1, s2 509# CHECK-INSTR: cv.avgu.sc.h s0, s1, s2 510# CHECK-ENCODING: [0x7b,0xc4,0x24,0x19] 511# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 512 513//===----------------------------------------------------------------------===// 514// cv.avgu.sc.b 515//===----------------------------------------------------------------------===// 516 517cv.avgu.sc.b t0, t1, t2 518# CHECK-INSTR: cv.avgu.sc.b t0, t1, t2 519# CHECK-ENCODING: [0xfb,0x52,0x73,0x18] 520# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 521 522cv.avgu.sc.b t3, t4, t5 523# CHECK-INSTR: cv.avgu.sc.b t3, t4, t5 524# CHECK-ENCODING: [0x7b,0xde,0xee,0x19] 525# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 526 527cv.avgu.sc.b a0, a1, a2 528# CHECK-INSTR: cv.avgu.sc.b a0, a1, a2 529# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x18] 530# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 531 532cv.avgu.sc.b s0, s1, s2 533# CHECK-INSTR: cv.avgu.sc.b s0, s1, s2 534# CHECK-ENCODING: [0x7b,0xd4,0x24,0x19] 535# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 536 537//===----------------------------------------------------------------------===// 538// cv.avgu.sci.h 539//===----------------------------------------------------------------------===// 540 541cv.avgu.sci.h t0, t1, 0 542# CHECK-INSTR: cv.avgu.sci.h t0, t1, 0 543# CHECK-ENCODING: [0xfb,0x62,0x03,0x18] 544# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 545 546cv.avgu.sci.h t3, t4, 32 547# CHECK-INSTR: cv.avgu.sci.h t3, t4, 32 548# CHECK-ENCODING: [0x7b,0xee,0x0e,0x19] 549# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 550 551cv.avgu.sci.h a0, a1, 7 552# CHECK-INSTR: cv.avgu.sci.h a0, a1, 7 553# CHECK-ENCODING: [0x7b,0xe5,0x35,0x1a] 554# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 555 556cv.avgu.sci.h s0, s1, 63 557# CHECK-INSTR: cv.avgu.sci.h s0, s1, 63 558# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x1b] 559# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 560 561//===----------------------------------------------------------------------===// 562// cv.avgu.sci.b 563//===----------------------------------------------------------------------===// 564 565cv.avgu.sci.b t0, t1, 0 566# CHECK-INSTR: cv.avgu.sci.b t0, t1, 0 567# CHECK-ENCODING: [0xfb,0x72,0x03,0x18] 568# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 569 570cv.avgu.sci.b t3, t4, 32 571# CHECK-INSTR: cv.avgu.sci.b t3, t4, 32 572# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x19] 573# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 574 575cv.avgu.sci.b a0, a1, 7 576# CHECK-INSTR: cv.avgu.sci.b a0, a1, 7 577# CHECK-ENCODING: [0x7b,0xf5,0x35,0x1a] 578# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 579 580cv.avgu.sci.b s0, s1, 63 581# CHECK-INSTR: cv.avgu.sci.b s0, s1, 63 582# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x1b] 583# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 584 585//===----------------------------------------------------------------------===// 586// cv.min.h 587//===----------------------------------------------------------------------===// 588 589cv.min.h t0, t1, t2 590# CHECK-INSTR: cv.min.h t0, t1, t2 591# CHECK-ENCODING: [0xfb,0x02,0x73,0x20] 592# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 593 594cv.min.h t3, t4, t5 595# CHECK-INSTR: cv.min.h t3, t4, t5 596# CHECK-ENCODING: [0x7b,0x8e,0xee,0x21] 597# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 598 599cv.min.h a0, a1, a2 600# CHECK-INSTR: cv.min.h a0, a1, a2 601# CHECK-ENCODING: [0x7b,0x85,0xc5,0x20] 602# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 603 604cv.min.h s0, s1, s2 605# CHECK-INSTR: cv.min.h s0, s1, s2 606# CHECK-ENCODING: [0x7b,0x84,0x24,0x21] 607# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 608 609//===----------------------------------------------------------------------===// 610// cv.min.b 611//===----------------------------------------------------------------------===// 612 613cv.min.b t0, t1, t2 614# CHECK-INSTR: cv.min.b t0, t1, t2 615# CHECK-ENCODING: [0xfb,0x12,0x73,0x20] 616# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 617 618cv.min.b t3, t4, t5 619# CHECK-INSTR: cv.min.b t3, t4, t5 620# CHECK-ENCODING: [0x7b,0x9e,0xee,0x21] 621# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 622 623cv.min.b a0, a1, a2 624# CHECK-INSTR: cv.min.b a0, a1, a2 625# CHECK-ENCODING: [0x7b,0x95,0xc5,0x20] 626# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 627 628cv.min.b s0, s1, s2 629# CHECK-INSTR: cv.min.b s0, s1, s2 630# CHECK-ENCODING: [0x7b,0x94,0x24,0x21] 631# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 632 633//===----------------------------------------------------------------------===// 634// cv.min.sc.h 635//===----------------------------------------------------------------------===// 636 637cv.min.sc.h t0, t1, t2 638# CHECK-INSTR: cv.min.sc.h t0, t1, t2 639# CHECK-ENCODING: [0xfb,0x42,0x73,0x20] 640# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 641 642cv.min.sc.h t3, t4, t5 643# CHECK-INSTR: cv.min.sc.h t3, t4, t5 644# CHECK-ENCODING: [0x7b,0xce,0xee,0x21] 645# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 646 647cv.min.sc.h a0, a1, a2 648# CHECK-INSTR: cv.min.sc.h a0, a1, a2 649# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x20] 650# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 651 652cv.min.sc.h s0, s1, s2 653# CHECK-INSTR: cv.min.sc.h s0, s1, s2 654# CHECK-ENCODING: [0x7b,0xc4,0x24,0x21] 655# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 656 657//===----------------------------------------------------------------------===// 658// cv.min.sc.b 659//===----------------------------------------------------------------------===// 660 661cv.min.sc.b t0, t1, t2 662# CHECK-INSTR: cv.min.sc.b t0, t1, t2 663# CHECK-ENCODING: [0xfb,0x52,0x73,0x20] 664# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 665 666cv.min.sc.b t3, t4, t5 667# CHECK-INSTR: cv.min.sc.b t3, t4, t5 668# CHECK-ENCODING: [0x7b,0xde,0xee,0x21] 669# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 670 671cv.min.sc.b a0, a1, a2 672# CHECK-INSTR: cv.min.sc.b a0, a1, a2 673# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x20] 674# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 675 676cv.min.sc.b s0, s1, s2 677# CHECK-INSTR: cv.min.sc.b s0, s1, s2 678# CHECK-ENCODING: [0x7b,0xd4,0x24,0x21] 679# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 680 681//===----------------------------------------------------------------------===// 682// cv.min.sci.h 683//===----------------------------------------------------------------------===// 684 685cv.min.sci.h t0, t1, 0 686# CHECK-INSTR: cv.min.sci.h t0, t1, 0 687# CHECK-ENCODING: [0xfb,0x62,0x03,0x20] 688# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 689 690cv.min.sci.h t3, t4, -32 691# CHECK-INSTR: cv.min.sci.h t3, t4, -32 692# CHECK-ENCODING: [0x7b,0xee,0x0e,0x21] 693# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 694 695cv.min.sci.h a0, a1, 7 696# CHECK-INSTR: cv.min.sci.h a0, a1, 7 697# CHECK-ENCODING: [0x7b,0xe5,0x35,0x22] 698# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 699 700cv.min.sci.h s0, s1, -1 701# CHECK-INSTR: cv.min.sci.h s0, s1, -1 702# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x23] 703# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 704 705//===----------------------------------------------------------------------===// 706// cv.min.sci.b 707//===----------------------------------------------------------------------===// 708 709cv.min.sci.b t0, t1, 0 710# CHECK-INSTR: cv.min.sci.b t0, t1, 0 711# CHECK-ENCODING: [0xfb,0x72,0x03,0x20] 712# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 713 714cv.min.sci.b t3, t4, -32 715# CHECK-INSTR: cv.min.sci.b t3, t4, -32 716# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x21] 717# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 718 719cv.min.sci.b a0, a1, 7 720# CHECK-INSTR: cv.min.sci.b a0, a1, 7 721# CHECK-ENCODING: [0x7b,0xf5,0x35,0x22] 722# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 723 724cv.min.sci.b s0, s1, -1 725# CHECK-INSTR: cv.min.sci.b s0, s1, -1 726# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x23] 727# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 728 729//===----------------------------------------------------------------------===// 730// cv.minu.h 731//===----------------------------------------------------------------------===// 732 733cv.minu.h t0, t1, t2 734# CHECK-INSTR: cv.minu.h t0, t1, t2 735# CHECK-ENCODING: [0xfb,0x02,0x73,0x28] 736# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 737 738cv.minu.h t3, t4, t5 739# CHECK-INSTR: cv.minu.h t3, t4, t5 740# CHECK-ENCODING: [0x7b,0x8e,0xee,0x29] 741# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 742 743cv.minu.h a0, a1, a2 744# CHECK-INSTR: cv.minu.h a0, a1, a2 745# CHECK-ENCODING: [0x7b,0x85,0xc5,0x28] 746# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 747 748cv.minu.h s0, s1, s2 749# CHECK-INSTR: cv.minu.h s0, s1, s2 750# CHECK-ENCODING: [0x7b,0x84,0x24,0x29] 751# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 752 753//===----------------------------------------------------------------------===// 754// cv.minu.b 755//===----------------------------------------------------------------------===// 756 757cv.minu.b t0, t1, t2 758# CHECK-INSTR: cv.minu.b t0, t1, t2 759# CHECK-ENCODING: [0xfb,0x12,0x73,0x28] 760# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 761 762cv.minu.b t3, t4, t5 763# CHECK-INSTR: cv.minu.b t3, t4, t5 764# CHECK-ENCODING: [0x7b,0x9e,0xee,0x29] 765# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 766 767cv.minu.b a0, a1, a2 768# CHECK-INSTR: cv.minu.b a0, a1, a2 769# CHECK-ENCODING: [0x7b,0x95,0xc5,0x28] 770# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 771 772cv.minu.b s0, s1, s2 773# CHECK-INSTR: cv.minu.b s0, s1, s2 774# CHECK-ENCODING: [0x7b,0x94,0x24,0x29] 775# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 776 777//===----------------------------------------------------------------------===// 778// cv.minu.sc.h 779//===----------------------------------------------------------------------===// 780 781cv.minu.sc.h t0, t1, t2 782# CHECK-INSTR: cv.minu.sc.h t0, t1, t2 783# CHECK-ENCODING: [0xfb,0x42,0x73,0x28] 784# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 785 786cv.minu.sc.h t3, t4, t5 787# CHECK-INSTR: cv.minu.sc.h t3, t4, t5 788# CHECK-ENCODING: [0x7b,0xce,0xee,0x29] 789# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 790 791cv.minu.sc.h a0, a1, a2 792# CHECK-INSTR: cv.minu.sc.h a0, a1, a2 793# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x28] 794# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 795 796cv.minu.sc.h s0, s1, s2 797# CHECK-INSTR: cv.minu.sc.h s0, s1, s2 798# CHECK-ENCODING: [0x7b,0xc4,0x24,0x29] 799# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 800 801//===----------------------------------------------------------------------===// 802// cv.minu.sc.b 803//===----------------------------------------------------------------------===// 804 805cv.minu.sc.b t0, t1, t2 806# CHECK-INSTR: cv.minu.sc.b t0, t1, t2 807# CHECK-ENCODING: [0xfb,0x52,0x73,0x28] 808# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 809 810cv.minu.sc.b t3, t4, t5 811# CHECK-INSTR: cv.minu.sc.b t3, t4, t5 812# CHECK-ENCODING: [0x7b,0xde,0xee,0x29] 813# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 814 815cv.minu.sc.b a0, a1, a2 816# CHECK-INSTR: cv.minu.sc.b a0, a1, a2 817# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x28] 818# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 819 820cv.minu.sc.b s0, s1, s2 821# CHECK-INSTR: cv.minu.sc.b s0, s1, s2 822# CHECK-ENCODING: [0x7b,0xd4,0x24,0x29] 823# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 824 825//===----------------------------------------------------------------------===// 826// cv.minu.sci.h 827//===----------------------------------------------------------------------===// 828 829cv.minu.sci.h t0, t1, 0 830# CHECK-INSTR: cv.minu.sci.h t0, t1, 0 831# CHECK-ENCODING: [0xfb,0x62,0x03,0x28] 832# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 833 834cv.minu.sci.h t3, t4, 32 835# CHECK-INSTR: cv.minu.sci.h t3, t4, 32 836# CHECK-ENCODING: [0x7b,0xee,0x0e,0x29] 837# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 838 839cv.minu.sci.h a0, a1, 7 840# CHECK-INSTR: cv.minu.sci.h a0, a1, 7 841# CHECK-ENCODING: [0x7b,0xe5,0x35,0x2a] 842# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 843 844cv.minu.sci.h s0, s1, 63 845# CHECK-INSTR: cv.minu.sci.h s0, s1, 63 846# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x2b] 847# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 848 849//===----------------------------------------------------------------------===// 850// cv.minu.sci.b 851//===----------------------------------------------------------------------===// 852 853cv.minu.sci.b t0, t1, 0 854# CHECK-INSTR: cv.minu.sci.b t0, t1, 0 855# CHECK-ENCODING: [0xfb,0x72,0x03,0x28] 856# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 857 858cv.minu.sci.b t3, t4, 32 859# CHECK-INSTR: cv.minu.sci.b t3, t4, 32 860# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x29] 861# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 862 863cv.minu.sci.b a0, a1, 7 864# CHECK-INSTR: cv.minu.sci.b a0, a1, 7 865# CHECK-ENCODING: [0x7b,0xf5,0x35,0x2a] 866# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 867 868cv.minu.sci.b s0, s1, 63 869# CHECK-INSTR: cv.minu.sci.b s0, s1, 63 870# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x2b] 871# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 872 873//===----------------------------------------------------------------------===// 874// cv.max.h 875//===----------------------------------------------------------------------===// 876 877cv.max.h t0, t1, t2 878# CHECK-INSTR: cv.max.h t0, t1, t2 879# CHECK-ENCODING: [0xfb,0x02,0x73,0x30] 880# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 881 882cv.max.h t3, t4, t5 883# CHECK-INSTR: cv.max.h t3, t4, t5 884# CHECK-ENCODING: [0x7b,0x8e,0xee,0x31] 885# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 886 887cv.max.h a0, a1, a2 888# CHECK-INSTR: cv.max.h a0, a1, a2 889# CHECK-ENCODING: [0x7b,0x85,0xc5,0x30] 890# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 891 892cv.max.h s0, s1, s2 893# CHECK-INSTR: cv.max.h s0, s1, s2 894# CHECK-ENCODING: [0x7b,0x84,0x24,0x31] 895# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 896 897//===----------------------------------------------------------------------===// 898// cv.max.b 899//===----------------------------------------------------------------------===// 900 901cv.max.b t0, t1, t2 902# CHECK-INSTR: cv.max.b t0, t1, t2 903# CHECK-ENCODING: [0xfb,0x12,0x73,0x30] 904# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 905 906cv.max.b t3, t4, t5 907# CHECK-INSTR: cv.max.b t3, t4, t5 908# CHECK-ENCODING: [0x7b,0x9e,0xee,0x31] 909# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 910 911cv.max.b a0, a1, a2 912# CHECK-INSTR: cv.max.b a0, a1, a2 913# CHECK-ENCODING: [0x7b,0x95,0xc5,0x30] 914# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 915 916cv.max.b s0, s1, s2 917# CHECK-INSTR: cv.max.b s0, s1, s2 918# CHECK-ENCODING: [0x7b,0x94,0x24,0x31] 919# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 920 921//===----------------------------------------------------------------------===// 922// cv.max.sc.h 923//===----------------------------------------------------------------------===// 924 925cv.max.sc.h t0, t1, t2 926# CHECK-INSTR: cv.max.sc.h t0, t1, t2 927# CHECK-ENCODING: [0xfb,0x42,0x73,0x30] 928# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 929 930cv.max.sc.h t3, t4, t5 931# CHECK-INSTR: cv.max.sc.h t3, t4, t5 932# CHECK-ENCODING: [0x7b,0xce,0xee,0x31] 933# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 934 935cv.max.sc.h a0, a1, a2 936# CHECK-INSTR: cv.max.sc.h a0, a1, a2 937# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x30] 938# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 939 940cv.max.sc.h s0, s1, s2 941# CHECK-INSTR: cv.max.sc.h s0, s1, s2 942# CHECK-ENCODING: [0x7b,0xc4,0x24,0x31] 943# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 944 945//===----------------------------------------------------------------------===// 946// cv.max.sc.b 947//===----------------------------------------------------------------------===// 948 949cv.max.sc.b t0, t1, t2 950# CHECK-INSTR: cv.max.sc.b t0, t1, t2 951# CHECK-ENCODING: [0xfb,0x52,0x73,0x30] 952# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 953 954cv.max.sc.b t3, t4, t5 955# CHECK-INSTR: cv.max.sc.b t3, t4, t5 956# CHECK-ENCODING: [0x7b,0xde,0xee,0x31] 957# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 958 959cv.max.sc.b a0, a1, a2 960# CHECK-INSTR: cv.max.sc.b a0, a1, a2 961# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x30] 962# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 963 964cv.max.sc.b s0, s1, s2 965# CHECK-INSTR: cv.max.sc.b s0, s1, s2 966# CHECK-ENCODING: [0x7b,0xd4,0x24,0x31] 967# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 968 969//===----------------------------------------------------------------------===// 970// cv.max.sci.h 971//===----------------------------------------------------------------------===// 972 973cv.max.sci.h t0, t1, 0 974# CHECK-INSTR: cv.max.sci.h t0, t1, 0 975# CHECK-ENCODING: [0xfb,0x62,0x03,0x30] 976# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 977 978cv.max.sci.h t3, t4, -32 979# CHECK-INSTR: cv.max.sci.h t3, t4, -32 980# CHECK-ENCODING: [0x7b,0xee,0x0e,0x31] 981# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 982 983cv.max.sci.h a0, a1, 7 984# CHECK-INSTR: cv.max.sci.h a0, a1, 7 985# CHECK-ENCODING: [0x7b,0xe5,0x35,0x32] 986# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 987 988cv.max.sci.h s0, s1, -1 989# CHECK-INSTR: cv.max.sci.h s0, s1, -1 990# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x33] 991# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 992 993//===----------------------------------------------------------------------===// 994// cv.max.sci.b 995//===----------------------------------------------------------------------===// 996 997cv.max.sci.b t0, t1, 0 998# CHECK-INSTR: cv.max.sci.b t0, t1, 0 999# CHECK-ENCODING: [0xfb,0x72,0x03,0x30] 1000# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1001 1002cv.max.sci.b t3, t4, -32 1003# CHECK-INSTR: cv.max.sci.b t3, t4, -32 1004# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x31] 1005# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1006 1007cv.max.sci.b a0, a1, 7 1008# CHECK-INSTR: cv.max.sci.b a0, a1, 7 1009# CHECK-ENCODING: [0x7b,0xf5,0x35,0x32] 1010# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1011 1012cv.max.sci.b s0, s1, -1 1013# CHECK-INSTR: cv.max.sci.b s0, s1, -1 1014# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x33] 1015# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1016 1017//===----------------------------------------------------------------------===// 1018// cv.maxu.h 1019//===----------------------------------------------------------------------===// 1020 1021cv.maxu.h t0, t1, t2 1022# CHECK-INSTR: cv.maxu.h t0, t1, t2 1023# CHECK-ENCODING: [0xfb,0x02,0x73,0x38] 1024# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1025 1026cv.maxu.h t3, t4, t5 1027# CHECK-INSTR: cv.maxu.h t3, t4, t5 1028# CHECK-ENCODING: [0x7b,0x8e,0xee,0x39] 1029# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1030 1031cv.maxu.h a0, a1, a2 1032# CHECK-INSTR: cv.maxu.h a0, a1, a2 1033# CHECK-ENCODING: [0x7b,0x85,0xc5,0x38] 1034# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1035 1036cv.maxu.h s0, s1, s2 1037# CHECK-INSTR: cv.maxu.h s0, s1, s2 1038# CHECK-ENCODING: [0x7b,0x84,0x24,0x39] 1039# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1040 1041//===----------------------------------------------------------------------===// 1042// cv.maxu.b 1043//===----------------------------------------------------------------------===// 1044 1045cv.maxu.b t0, t1, t2 1046# CHECK-INSTR: cv.maxu.b t0, t1, t2 1047# CHECK-ENCODING: [0xfb,0x12,0x73,0x38] 1048# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1049 1050cv.maxu.b t3, t4, t5 1051# CHECK-INSTR: cv.maxu.b t3, t4, t5 1052# CHECK-ENCODING: [0x7b,0x9e,0xee,0x39] 1053# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1054 1055cv.maxu.b a0, a1, a2 1056# CHECK-INSTR: cv.maxu.b a0, a1, a2 1057# CHECK-ENCODING: [0x7b,0x95,0xc5,0x38] 1058# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1059 1060cv.maxu.b s0, s1, s2 1061# CHECK-INSTR: cv.maxu.b s0, s1, s2 1062# CHECK-ENCODING: [0x7b,0x94,0x24,0x39] 1063# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1064 1065//===----------------------------------------------------------------------===// 1066// cv.maxu.sc.h 1067//===----------------------------------------------------------------------===// 1068 1069cv.maxu.sc.h t0, t1, t2 1070# CHECK-INSTR: cv.maxu.sc.h t0, t1, t2 1071# CHECK-ENCODING: [0xfb,0x42,0x73,0x38] 1072# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1073 1074cv.maxu.sc.h t3, t4, t5 1075# CHECK-INSTR: cv.maxu.sc.h t3, t4, t5 1076# CHECK-ENCODING: [0x7b,0xce,0xee,0x39] 1077# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1078 1079cv.maxu.sc.h a0, a1, a2 1080# CHECK-INSTR: cv.maxu.sc.h a0, a1, a2 1081# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x38] 1082# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1083 1084cv.maxu.sc.h s0, s1, s2 1085# CHECK-INSTR: cv.maxu.sc.h s0, s1, s2 1086# CHECK-ENCODING: [0x7b,0xc4,0x24,0x39] 1087# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1088 1089//===----------------------------------------------------------------------===// 1090// cv.maxu.sc.b 1091//===----------------------------------------------------------------------===// 1092 1093cv.maxu.sc.b t0, t1, t2 1094# CHECK-INSTR: cv.maxu.sc.b t0, t1, t2 1095# CHECK-ENCODING: [0xfb,0x52,0x73,0x38] 1096# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1097 1098cv.maxu.sc.b t3, t4, t5 1099# CHECK-INSTR: cv.maxu.sc.b t3, t4, t5 1100# CHECK-ENCODING: [0x7b,0xde,0xee,0x39] 1101# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1102 1103cv.maxu.sc.b a0, a1, a2 1104# CHECK-INSTR: cv.maxu.sc.b a0, a1, a2 1105# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x38] 1106# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1107 1108cv.maxu.sc.b s0, s1, s2 1109# CHECK-INSTR: cv.maxu.sc.b s0, s1, s2 1110# CHECK-ENCODING: [0x7b,0xd4,0x24,0x39] 1111# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1112 1113//===----------------------------------------------------------------------===// 1114// cv.maxu.sci.h 1115//===----------------------------------------------------------------------===// 1116 1117cv.maxu.sci.h t0, t1, 0 1118# CHECK-INSTR: cv.maxu.sci.h t0, t1, 0 1119# CHECK-ENCODING: [0xfb,0x62,0x03,0x38] 1120# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1121 1122cv.maxu.sci.h t3, t4, 32 1123# CHECK-INSTR: cv.maxu.sci.h t3, t4, 32 1124# CHECK-ENCODING: [0x7b,0xee,0x0e,0x39] 1125# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1126 1127cv.maxu.sci.h a0, a1, 7 1128# CHECK-INSTR: cv.maxu.sci.h a0, a1, 7 1129# CHECK-ENCODING: [0x7b,0xe5,0x35,0x3a] 1130# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1131 1132cv.maxu.sci.h s0, s1, 63 1133# CHECK-INSTR: cv.maxu.sci.h s0, s1, 63 1134# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x3b] 1135# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1136 1137//===----------------------------------------------------------------------===// 1138// cv.maxu.sci.b 1139//===----------------------------------------------------------------------===// 1140 1141cv.maxu.sci.b t0, t1, 0 1142# CHECK-INSTR: cv.maxu.sci.b t0, t1, 0 1143# CHECK-ENCODING: [0xfb,0x72,0x03,0x38] 1144# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1145 1146cv.maxu.sci.b t3, t4, 32 1147# CHECK-INSTR: cv.maxu.sci.b t3, t4, 32 1148# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x39] 1149# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1150 1151cv.maxu.sci.b a0, a1, 7 1152# CHECK-INSTR: cv.maxu.sci.b a0, a1, 7 1153# CHECK-ENCODING: [0x7b,0xf5,0x35,0x3a] 1154# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1155 1156cv.maxu.sci.b s0, s1, 63 1157# CHECK-INSTR: cv.maxu.sci.b s0, s1, 63 1158# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x3b] 1159# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1160 1161//===----------------------------------------------------------------------===// 1162// cv.srl.h 1163//===----------------------------------------------------------------------===// 1164 1165cv.srl.h t0, t1, t2 1166# CHECK-INSTR: cv.srl.h t0, t1, t2 1167# CHECK-ENCODING: [0xfb,0x02,0x73,0x40] 1168# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1169 1170cv.srl.h t3, t4, t5 1171# CHECK-INSTR: cv.srl.h t3, t4, t5 1172# CHECK-ENCODING: [0x7b,0x8e,0xee,0x41] 1173# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1174 1175cv.srl.h a0, a1, a2 1176# CHECK-INSTR: cv.srl.h a0, a1, a2 1177# CHECK-ENCODING: [0x7b,0x85,0xc5,0x40] 1178# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1179 1180cv.srl.h s0, s1, s2 1181# CHECK-INSTR: cv.srl.h s0, s1, s2 1182# CHECK-ENCODING: [0x7b,0x84,0x24,0x41] 1183# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1184 1185//===----------------------------------------------------------------------===// 1186// cv.srl.b 1187//===----------------------------------------------------------------------===// 1188 1189cv.srl.b t0, t1, t2 1190# CHECK-INSTR: cv.srl.b t0, t1, t2 1191# CHECK-ENCODING: [0xfb,0x12,0x73,0x40] 1192# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1193 1194cv.srl.b t3, t4, t5 1195# CHECK-INSTR: cv.srl.b t3, t4, t5 1196# CHECK-ENCODING: [0x7b,0x9e,0xee,0x41] 1197# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1198 1199cv.srl.b a0, a1, a2 1200# CHECK-INSTR: cv.srl.b a0, a1, a2 1201# CHECK-ENCODING: [0x7b,0x95,0xc5,0x40] 1202# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1203 1204cv.srl.b s0, s1, s2 1205# CHECK-INSTR: cv.srl.b s0, s1, s2 1206# CHECK-ENCODING: [0x7b,0x94,0x24,0x41] 1207# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1208 1209//===----------------------------------------------------------------------===// 1210// cv.srl.sc.h 1211//===----------------------------------------------------------------------===// 1212 1213cv.srl.sc.h t0, t1, t2 1214# CHECK-INSTR: cv.srl.sc.h t0, t1, t2 1215# CHECK-ENCODING: [0xfb,0x42,0x73,0x40] 1216# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1217 1218cv.srl.sc.h t3, t4, t5 1219# CHECK-INSTR: cv.srl.sc.h t3, t4, t5 1220# CHECK-ENCODING: [0x7b,0xce,0xee,0x41] 1221# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1222 1223cv.srl.sc.h a0, a1, a2 1224# CHECK-INSTR: cv.srl.sc.h a0, a1, a2 1225# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x40] 1226# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1227 1228cv.srl.sc.h s0, s1, s2 1229# CHECK-INSTR: cv.srl.sc.h s0, s1, s2 1230# CHECK-ENCODING: [0x7b,0xc4,0x24,0x41] 1231# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1232 1233//===----------------------------------------------------------------------===// 1234// cv.srl.sc.b 1235//===----------------------------------------------------------------------===// 1236 1237cv.srl.sc.b t0, t1, t2 1238# CHECK-INSTR: cv.srl.sc.b t0, t1, t2 1239# CHECK-ENCODING: [0xfb,0x52,0x73,0x40] 1240# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1241 1242cv.srl.sc.b t3, t4, t5 1243# CHECK-INSTR: cv.srl.sc.b t3, t4, t5 1244# CHECK-ENCODING: [0x7b,0xde,0xee,0x41] 1245# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1246 1247cv.srl.sc.b a0, a1, a2 1248# CHECK-INSTR: cv.srl.sc.b a0, a1, a2 1249# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x40] 1250# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1251 1252cv.srl.sc.b s0, s1, s2 1253# CHECK-INSTR: cv.srl.sc.b s0, s1, s2 1254# CHECK-ENCODING: [0x7b,0xd4,0x24,0x41] 1255# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1256 1257//===----------------------------------------------------------------------===// 1258// cv.srl.sci.h 1259//===----------------------------------------------------------------------===// 1260 1261cv.srl.sci.h t0, t1, 0 1262# CHECK-INSTR: cv.srl.sci.h t0, t1, 0 1263# CHECK-ENCODING: [0xfb,0x62,0x03,0x40] 1264# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1265 1266cv.srl.sci.h t3, t4, 0 1267# CHECK-INSTR: cv.srl.sci.h t3, t4, 0 1268# CHECK-ENCODING: [0x7b,0xee,0x0e,0x40] 1269# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1270 1271cv.srl.sci.h a0, a1, 7 1272# CHECK-INSTR: cv.srl.sci.h a0, a1, 7 1273# CHECK-ENCODING: [0x7b,0xe5,0x35,0x42] 1274# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1275 1276cv.srl.sci.h s0, s1, 15 1277# CHECK-INSTR: cv.srl.sci.h s0, s1, 15 1278# CHECK-ENCODING: [0x7b,0xe4,0x74,0x42] 1279# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1280 1281//===----------------------------------------------------------------------===// 1282// cv.srl.sci.b 1283//===----------------------------------------------------------------------===// 1284 1285cv.srl.sci.b t0, t1, 0 1286# CHECK-INSTR: cv.srl.sci.b t0, t1, 0 1287# CHECK-ENCODING: [0xfb,0x72,0x03,0x40] 1288# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1289 1290cv.srl.sci.b t3, t4, 0 1291# CHECK-INSTR: cv.srl.sci.b t3, t4, 0 1292# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x40] 1293# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1294 1295cv.srl.sci.b a0, a1, 7 1296# CHECK-INSTR: cv.srl.sci.b a0, a1, 7 1297# CHECK-ENCODING: [0x7b,0xf5,0x35,0x42] 1298# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1299 1300cv.srl.sci.b s0, s1, 7 1301# CHECK-INSTR: cv.srl.sci.b s0, s1, 7 1302# CHECK-ENCODING: [0x7b,0xf4,0x34,0x42] 1303# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1304 1305//===----------------------------------------------------------------------===// 1306// cv.sra.h 1307//===----------------------------------------------------------------------===// 1308 1309cv.sra.h t0, t1, t2 1310# CHECK-INSTR: cv.sra.h t0, t1, t2 1311# CHECK-ENCODING: [0xfb,0x02,0x73,0x48] 1312# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1313 1314cv.sra.h t3, t4, t5 1315# CHECK-INSTR: cv.sra.h t3, t4, t5 1316# CHECK-ENCODING: [0x7b,0x8e,0xee,0x49] 1317# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1318 1319cv.sra.h a0, a1, a2 1320# CHECK-INSTR: cv.sra.h a0, a1, a2 1321# CHECK-ENCODING: [0x7b,0x85,0xc5,0x48] 1322# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1323 1324cv.sra.h s0, s1, s2 1325# CHECK-INSTR: cv.sra.h s0, s1, s2 1326# CHECK-ENCODING: [0x7b,0x84,0x24,0x49] 1327# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1328 1329//===----------------------------------------------------------------------===// 1330// cv.sra.b 1331//===----------------------------------------------------------------------===// 1332 1333cv.sra.b t0, t1, t2 1334# CHECK-INSTR: cv.sra.b t0, t1, t2 1335# CHECK-ENCODING: [0xfb,0x12,0x73,0x48] 1336# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1337 1338cv.sra.b t3, t4, t5 1339# CHECK-INSTR: cv.sra.b t3, t4, t5 1340# CHECK-ENCODING: [0x7b,0x9e,0xee,0x49] 1341# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1342 1343cv.sra.b a0, a1, a2 1344# CHECK-INSTR: cv.sra.b a0, a1, a2 1345# CHECK-ENCODING: [0x7b,0x95,0xc5,0x48] 1346# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1347 1348cv.sra.b s0, s1, s2 1349# CHECK-INSTR: cv.sra.b s0, s1, s2 1350# CHECK-ENCODING: [0x7b,0x94,0x24,0x49] 1351# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1352 1353//===----------------------------------------------------------------------===// 1354// cv.sra.sc.h 1355//===----------------------------------------------------------------------===// 1356 1357cv.sra.sc.h t0, t1, t2 1358# CHECK-INSTR: cv.sra.sc.h t0, t1, t2 1359# CHECK-ENCODING: [0xfb,0x42,0x73,0x48] 1360# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1361 1362cv.sra.sc.h t3, t4, t5 1363# CHECK-INSTR: cv.sra.sc.h t3, t4, t5 1364# CHECK-ENCODING: [0x7b,0xce,0xee,0x49] 1365# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1366 1367cv.sra.sc.h a0, a1, a2 1368# CHECK-INSTR: cv.sra.sc.h a0, a1, a2 1369# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x48] 1370# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1371 1372cv.sra.sc.h s0, s1, s2 1373# CHECK-INSTR: cv.sra.sc.h s0, s1, s2 1374# CHECK-ENCODING: [0x7b,0xc4,0x24,0x49] 1375# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1376 1377//===----------------------------------------------------------------------===// 1378// cv.sra.sc.b 1379//===----------------------------------------------------------------------===// 1380 1381cv.sra.sc.b t0, t1, t2 1382# CHECK-INSTR: cv.sra.sc.b t0, t1, t2 1383# CHECK-ENCODING: [0xfb,0x52,0x73,0x48] 1384# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1385 1386cv.sra.sc.b t3, t4, t5 1387# CHECK-INSTR: cv.sra.sc.b t3, t4, t5 1388# CHECK-ENCODING: [0x7b,0xde,0xee,0x49] 1389# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1390 1391cv.sra.sc.b a0, a1, a2 1392# CHECK-INSTR: cv.sra.sc.b a0, a1, a2 1393# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x48] 1394# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1395 1396cv.sra.sc.b s0, s1, s2 1397# CHECK-INSTR: cv.sra.sc.b s0, s1, s2 1398# CHECK-ENCODING: [0x7b,0xd4,0x24,0x49] 1399# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1400 1401//===----------------------------------------------------------------------===// 1402// cv.sra.sci.h 1403//===----------------------------------------------------------------------===// 1404 1405cv.sra.sci.h t0, t1, 0 1406# CHECK-INSTR: cv.sra.sci.h t0, t1, 0 1407# CHECK-ENCODING: [0xfb,0x62,0x03,0x48] 1408# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1409 1410cv.sra.sci.h t3, t4, 0 1411# CHECK-INSTR: cv.sra.sci.h t3, t4, 0 1412# CHECK-ENCODING: [0x7b,0xee,0x0e,0x48] 1413# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1414 1415cv.sra.sci.h a0, a1, 7 1416# CHECK-INSTR: cv.sra.sci.h a0, a1, 7 1417# CHECK-ENCODING: [0x7b,0xe5,0x35,0x4a] 1418# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1419 1420cv.sra.sci.h s0, s1, 15 1421# CHECK-INSTR: cv.sra.sci.h s0, s1, 15 1422# CHECK-ENCODING: [0x7b,0xe4,0x74,0x4a] 1423# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1424 1425//===----------------------------------------------------------------------===// 1426// cv.sra.sci.b 1427//===----------------------------------------------------------------------===// 1428 1429cv.sra.sci.b t0, t1, 0 1430# CHECK-INSTR: cv.sra.sci.b t0, t1, 0 1431# CHECK-ENCODING: [0xfb,0x72,0x03,0x48] 1432# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1433 1434cv.sra.sci.b t3, t4, 0 1435# CHECK-INSTR: cv.sra.sci.b t3, t4, 0 1436# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x48] 1437# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1438 1439cv.sra.sci.b a0, a1, 7 1440# CHECK-INSTR: cv.sra.sci.b a0, a1, 7 1441# CHECK-ENCODING: [0x7b,0xf5,0x35,0x4a] 1442# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1443 1444cv.sra.sci.b s0, s1, 7 1445# CHECK-INSTR: cv.sra.sci.b s0, s1, 7 1446# CHECK-ENCODING: [0x7b,0xf4,0x34,0x4a] 1447# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1448 1449//===----------------------------------------------------------------------===// 1450// cv.sll.h 1451//===----------------------------------------------------------------------===// 1452 1453cv.sll.h t0, t1, t2 1454# CHECK-INSTR: cv.sll.h t0, t1, t2 1455# CHECK-ENCODING: [0xfb,0x02,0x73,0x50] 1456# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1457 1458cv.sll.h t3, t4, t5 1459# CHECK-INSTR: cv.sll.h t3, t4, t5 1460# CHECK-ENCODING: [0x7b,0x8e,0xee,0x51] 1461# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1462 1463cv.sll.h a0, a1, a2 1464# CHECK-INSTR: cv.sll.h a0, a1, a2 1465# CHECK-ENCODING: [0x7b,0x85,0xc5,0x50] 1466# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1467 1468cv.sll.h s0, s1, s2 1469# CHECK-INSTR: cv.sll.h s0, s1, s2 1470# CHECK-ENCODING: [0x7b,0x84,0x24,0x51] 1471# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1472 1473//===----------------------------------------------------------------------===// 1474// cv.sll.b 1475//===----------------------------------------------------------------------===// 1476 1477cv.sll.b t0, t1, t2 1478# CHECK-INSTR: cv.sll.b t0, t1, t2 1479# CHECK-ENCODING: [0xfb,0x12,0x73,0x50] 1480# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1481 1482cv.sll.b t3, t4, t5 1483# CHECK-INSTR: cv.sll.b t3, t4, t5 1484# CHECK-ENCODING: [0x7b,0x9e,0xee,0x51] 1485# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1486 1487cv.sll.b a0, a1, a2 1488# CHECK-INSTR: cv.sll.b a0, a1, a2 1489# CHECK-ENCODING: [0x7b,0x95,0xc5,0x50] 1490# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1491 1492cv.sll.b s0, s1, s2 1493# CHECK-INSTR: cv.sll.b s0, s1, s2 1494# CHECK-ENCODING: [0x7b,0x94,0x24,0x51] 1495# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1496 1497//===----------------------------------------------------------------------===// 1498// cv.sll.sc.h 1499//===----------------------------------------------------------------------===// 1500 1501cv.sll.sc.h t0, t1, t2 1502# CHECK-INSTR: cv.sll.sc.h t0, t1, t2 1503# CHECK-ENCODING: [0xfb,0x42,0x73,0x50] 1504# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1505 1506cv.sll.sc.h t3, t4, t5 1507# CHECK-INSTR: cv.sll.sc.h t3, t4, t5 1508# CHECK-ENCODING: [0x7b,0xce,0xee,0x51] 1509# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1510 1511cv.sll.sc.h a0, a1, a2 1512# CHECK-INSTR: cv.sll.sc.h a0, a1, a2 1513# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x50] 1514# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1515 1516cv.sll.sc.h s0, s1, s2 1517# CHECK-INSTR: cv.sll.sc.h s0, s1, s2 1518# CHECK-ENCODING: [0x7b,0xc4,0x24,0x51] 1519# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1520 1521//===----------------------------------------------------------------------===// 1522// cv.sll.sc.b 1523//===----------------------------------------------------------------------===// 1524 1525cv.sll.sc.b t0, t1, t2 1526# CHECK-INSTR: cv.sll.sc.b t0, t1, t2 1527# CHECK-ENCODING: [0xfb,0x52,0x73,0x50] 1528# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1529 1530cv.sll.sc.b t3, t4, t5 1531# CHECK-INSTR: cv.sll.sc.b t3, t4, t5 1532# CHECK-ENCODING: [0x7b,0xde,0xee,0x51] 1533# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1534 1535cv.sll.sc.b a0, a1, a2 1536# CHECK-INSTR: cv.sll.sc.b a0, a1, a2 1537# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x50] 1538# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1539 1540cv.sll.sc.b s0, s1, s2 1541# CHECK-INSTR: cv.sll.sc.b s0, s1, s2 1542# CHECK-ENCODING: [0x7b,0xd4,0x24,0x51] 1543# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1544 1545//===----------------------------------------------------------------------===// 1546// cv.sll.sci.h 1547//===----------------------------------------------------------------------===// 1548 1549cv.sll.sci.h t0, t1, 0 1550# CHECK-INSTR: cv.sll.sci.h t0, t1, 0 1551# CHECK-ENCODING: [0xfb,0x62,0x03,0x50] 1552# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1553 1554cv.sll.sci.h t3, t4, 0 1555# CHECK-INSTR: cv.sll.sci.h t3, t4, 0 1556# CHECK-ENCODING: [0x7b,0xee,0x0e,0x50] 1557# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1558 1559cv.sll.sci.h a0, a1, 7 1560# CHECK-INSTR: cv.sll.sci.h a0, a1, 7 1561# CHECK-ENCODING: [0x7b,0xe5,0x35,0x52] 1562# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1563 1564cv.sll.sci.h s0, s1, 15 1565# CHECK-INSTR: cv.sll.sci.h s0, s1, 15 1566# CHECK-ENCODING: [0x7b,0xe4,0x74,0x52] 1567# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1568 1569//===----------------------------------------------------------------------===// 1570// cv.sll.sci.b 1571//===----------------------------------------------------------------------===// 1572 1573cv.sll.sci.b t0, t1, 0 1574# CHECK-INSTR: cv.sll.sci.b t0, t1, 0 1575# CHECK-ENCODING: [0xfb,0x72,0x03,0x50] 1576# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1577 1578cv.sll.sci.b t3, t4, 0 1579# CHECK-INSTR: cv.sll.sci.b t3, t4, 0 1580# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x50] 1581# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1582 1583cv.sll.sci.b a0, a1, 7 1584# CHECK-INSTR: cv.sll.sci.b a0, a1, 7 1585# CHECK-ENCODING: [0x7b,0xf5,0x35,0x52] 1586# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1587 1588cv.sll.sci.b s0, s1, 7 1589# CHECK-INSTR: cv.sll.sci.b s0, s1, 7 1590# CHECK-ENCODING: [0x7b,0xf4,0x34,0x52] 1591# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1592 1593//===----------------------------------------------------------------------===// 1594// cv.or.h 1595//===----------------------------------------------------------------------===// 1596 1597cv.or.h t0, t1, t2 1598# CHECK-INSTR: cv.or.h t0, t1, t2 1599# CHECK-ENCODING: [0xfb,0x02,0x73,0x58] 1600# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1601 1602cv.or.h t3, t4, t5 1603# CHECK-INSTR: cv.or.h t3, t4, t5 1604# CHECK-ENCODING: [0x7b,0x8e,0xee,0x59] 1605# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1606 1607cv.or.h a0, a1, a2 1608# CHECK-INSTR: cv.or.h a0, a1, a2 1609# CHECK-ENCODING: [0x7b,0x85,0xc5,0x58] 1610# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1611 1612cv.or.h s0, s1, s2 1613# CHECK-INSTR: cv.or.h s0, s1, s2 1614# CHECK-ENCODING: [0x7b,0x84,0x24,0x59] 1615# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1616 1617//===----------------------------------------------------------------------===// 1618// cv.or.b 1619//===----------------------------------------------------------------------===// 1620 1621cv.or.b t0, t1, t2 1622# CHECK-INSTR: cv.or.b t0, t1, t2 1623# CHECK-ENCODING: [0xfb,0x12,0x73,0x58] 1624# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1625 1626cv.or.b t3, t4, t5 1627# CHECK-INSTR: cv.or.b t3, t4, t5 1628# CHECK-ENCODING: [0x7b,0x9e,0xee,0x59] 1629# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1630 1631cv.or.b a0, a1, a2 1632# CHECK-INSTR: cv.or.b a0, a1, a2 1633# CHECK-ENCODING: [0x7b,0x95,0xc5,0x58] 1634# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1635 1636cv.or.b s0, s1, s2 1637# CHECK-INSTR: cv.or.b s0, s1, s2 1638# CHECK-ENCODING: [0x7b,0x94,0x24,0x59] 1639# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1640 1641//===----------------------------------------------------------------------===// 1642// cv.or.sc.h 1643//===----------------------------------------------------------------------===// 1644 1645cv.or.sc.h t0, t1, t2 1646# CHECK-INSTR: cv.or.sc.h t0, t1, t2 1647# CHECK-ENCODING: [0xfb,0x42,0x73,0x58] 1648# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1649 1650cv.or.sc.h t3, t4, t5 1651# CHECK-INSTR: cv.or.sc.h t3, t4, t5 1652# CHECK-ENCODING: [0x7b,0xce,0xee,0x59] 1653# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1654 1655cv.or.sc.h a0, a1, a2 1656# CHECK-INSTR: cv.or.sc.h a0, a1, a2 1657# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x58] 1658# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1659 1660cv.or.sc.h s0, s1, s2 1661# CHECK-INSTR: cv.or.sc.h s0, s1, s2 1662# CHECK-ENCODING: [0x7b,0xc4,0x24,0x59] 1663# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1664 1665//===----------------------------------------------------------------------===// 1666// cv.or.sc.b 1667//===----------------------------------------------------------------------===// 1668 1669cv.or.sc.b t0, t1, t2 1670# CHECK-INSTR: cv.or.sc.b t0, t1, t2 1671# CHECK-ENCODING: [0xfb,0x52,0x73,0x58] 1672# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1673 1674cv.or.sc.b t3, t4, t5 1675# CHECK-INSTR: cv.or.sc.b t3, t4, t5 1676# CHECK-ENCODING: [0x7b,0xde,0xee,0x59] 1677# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1678 1679cv.or.sc.b a0, a1, a2 1680# CHECK-INSTR: cv.or.sc.b a0, a1, a2 1681# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x58] 1682# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1683 1684cv.or.sc.b s0, s1, s2 1685# CHECK-INSTR: cv.or.sc.b s0, s1, s2 1686# CHECK-ENCODING: [0x7b,0xd4,0x24,0x59] 1687# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1688 1689//===----------------------------------------------------------------------===// 1690// cv.or.sci.h 1691//===----------------------------------------------------------------------===// 1692 1693cv.or.sci.h t0, t1, 0 1694# CHECK-INSTR: cv.or.sci.h t0, t1, 0 1695# CHECK-ENCODING: [0xfb,0x62,0x03,0x58] 1696# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1697 1698cv.or.sci.h t3, t4, -32 1699# CHECK-INSTR: cv.or.sci.h t3, t4, -32 1700# CHECK-ENCODING: [0x7b,0xee,0x0e,0x59] 1701# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1702 1703cv.or.sci.h a0, a1, 7 1704# CHECK-INSTR: cv.or.sci.h a0, a1, 7 1705# CHECK-ENCODING: [0x7b,0xe5,0x35,0x5a] 1706# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1707 1708cv.or.sci.h s0, s1, -1 1709# CHECK-INSTR: cv.or.sci.h s0, s1, -1 1710# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x5b] 1711# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1712 1713//===----------------------------------------------------------------------===// 1714// cv.or.sci.b 1715//===----------------------------------------------------------------------===// 1716 1717cv.or.sci.b t0, t1, 0 1718# CHECK-INSTR: cv.or.sci.b t0, t1, 0 1719# CHECK-ENCODING: [0xfb,0x72,0x03,0x58] 1720# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1721 1722cv.or.sci.b t3, t4, -32 1723# CHECK-INSTR: cv.or.sci.b t3, t4, -32 1724# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x59] 1725# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1726 1727cv.or.sci.b a0, a1, 7 1728# CHECK-INSTR: cv.or.sci.b a0, a1, 7 1729# CHECK-ENCODING: [0x7b,0xf5,0x35,0x5a] 1730# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1731 1732cv.or.sci.b s0, s1, -1 1733# CHECK-INSTR: cv.or.sci.b s0, s1, -1 1734# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x5b] 1735# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1736 1737//===----------------------------------------------------------------------===// 1738// cv.xor.h 1739//===----------------------------------------------------------------------===// 1740 1741cv.xor.h t0, t1, t2 1742# CHECK-INSTR: cv.xor.h t0, t1, t2 1743# CHECK-ENCODING: [0xfb,0x02,0x73,0x60] 1744# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1745 1746cv.xor.h t3, t4, t5 1747# CHECK-INSTR: cv.xor.h t3, t4, t5 1748# CHECK-ENCODING: [0x7b,0x8e,0xee,0x61] 1749# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1750 1751cv.xor.h a0, a1, a2 1752# CHECK-INSTR: cv.xor.h a0, a1, a2 1753# CHECK-ENCODING: [0x7b,0x85,0xc5,0x60] 1754# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1755 1756cv.xor.h s0, s1, s2 1757# CHECK-INSTR: cv.xor.h s0, s1, s2 1758# CHECK-ENCODING: [0x7b,0x84,0x24,0x61] 1759# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1760 1761//===----------------------------------------------------------------------===// 1762// cv.xor.b 1763//===----------------------------------------------------------------------===// 1764 1765cv.xor.b t0, t1, t2 1766# CHECK-INSTR: cv.xor.b t0, t1, t2 1767# CHECK-ENCODING: [0xfb,0x12,0x73,0x60] 1768# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1769 1770cv.xor.b t3, t4, t5 1771# CHECK-INSTR: cv.xor.b t3, t4, t5 1772# CHECK-ENCODING: [0x7b,0x9e,0xee,0x61] 1773# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1774 1775cv.xor.b a0, a1, a2 1776# CHECK-INSTR: cv.xor.b a0, a1, a2 1777# CHECK-ENCODING: [0x7b,0x95,0xc5,0x60] 1778# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1779 1780cv.xor.b s0, s1, s2 1781# CHECK-INSTR: cv.xor.b s0, s1, s2 1782# CHECK-ENCODING: [0x7b,0x94,0x24,0x61] 1783# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1784 1785//===----------------------------------------------------------------------===// 1786// cv.xor.sc.h 1787//===----------------------------------------------------------------------===// 1788 1789cv.xor.sc.h t0, t1, t2 1790# CHECK-INSTR: cv.xor.sc.h t0, t1, t2 1791# CHECK-ENCODING: [0xfb,0x42,0x73,0x60] 1792# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1793 1794cv.xor.sc.h t3, t4, t5 1795# CHECK-INSTR: cv.xor.sc.h t3, t4, t5 1796# CHECK-ENCODING: [0x7b,0xce,0xee,0x61] 1797# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1798 1799cv.xor.sc.h a0, a1, a2 1800# CHECK-INSTR: cv.xor.sc.h a0, a1, a2 1801# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x60] 1802# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1803 1804cv.xor.sc.h s0, s1, s2 1805# CHECK-INSTR: cv.xor.sc.h s0, s1, s2 1806# CHECK-ENCODING: [0x7b,0xc4,0x24,0x61] 1807# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1808 1809//===----------------------------------------------------------------------===// 1810// cv.xor.sc.b 1811//===----------------------------------------------------------------------===// 1812 1813cv.xor.sc.b t0, t1, t2 1814# CHECK-INSTR: cv.xor.sc.b t0, t1, t2 1815# CHECK-ENCODING: [0xfb,0x52,0x73,0x60] 1816# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1817 1818cv.xor.sc.b t3, t4, t5 1819# CHECK-INSTR: cv.xor.sc.b t3, t4, t5 1820# CHECK-ENCODING: [0x7b,0xde,0xee,0x61] 1821# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1822 1823cv.xor.sc.b a0, a1, a2 1824# CHECK-INSTR: cv.xor.sc.b a0, a1, a2 1825# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x60] 1826# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1827 1828cv.xor.sc.b s0, s1, s2 1829# CHECK-INSTR: cv.xor.sc.b s0, s1, s2 1830# CHECK-ENCODING: [0x7b,0xd4,0x24,0x61] 1831# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1832 1833//===----------------------------------------------------------------------===// 1834// cv.xor.sci.h 1835//===----------------------------------------------------------------------===// 1836 1837cv.xor.sci.h t0, t1, 0 1838# CHECK-INSTR: cv.xor.sci.h t0, t1, 0 1839# CHECK-ENCODING: [0xfb,0x62,0x03,0x60] 1840# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1841 1842cv.xor.sci.h t3, t4, -32 1843# CHECK-INSTR: cv.xor.sci.h t3, t4, -32 1844# CHECK-ENCODING: [0x7b,0xee,0x0e,0x61] 1845# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1846 1847cv.xor.sci.h a0, a1, 7 1848# CHECK-INSTR: cv.xor.sci.h a0, a1, 7 1849# CHECK-ENCODING: [0x7b,0xe5,0x35,0x62] 1850# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1851 1852cv.xor.sci.h s0, s1, -1 1853# CHECK-INSTR: cv.xor.sci.h s0, s1, -1 1854# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x63] 1855# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1856 1857//===----------------------------------------------------------------------===// 1858// cv.xor.sci.b 1859//===----------------------------------------------------------------------===// 1860 1861cv.xor.sci.b t0, t1, 0 1862# CHECK-INSTR: cv.xor.sci.b t0, t1, 0 1863# CHECK-ENCODING: [0xfb,0x72,0x03,0x60] 1864# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1865 1866cv.xor.sci.b t3, t4, -32 1867# CHECK-INSTR: cv.xor.sci.b t3, t4, -32 1868# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x61] 1869# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1870 1871cv.xor.sci.b a0, a1, 7 1872# CHECK-INSTR: cv.xor.sci.b a0, a1, 7 1873# CHECK-ENCODING: [0x7b,0xf5,0x35,0x62] 1874# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1875 1876cv.xor.sci.b s0, s1, -1 1877# CHECK-INSTR: cv.xor.sci.b s0, s1, -1 1878# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x63] 1879# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1880 1881//===----------------------------------------------------------------------===// 1882// cv.and.h 1883//===----------------------------------------------------------------------===// 1884 1885cv.and.h t0, t1, t2 1886# CHECK-INSTR: cv.and.h t0, t1, t2 1887# CHECK-ENCODING: [0xfb,0x02,0x73,0x68] 1888# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1889 1890cv.and.h t3, t4, t5 1891# CHECK-INSTR: cv.and.h t3, t4, t5 1892# CHECK-ENCODING: [0x7b,0x8e,0xee,0x69] 1893# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1894 1895cv.and.h a0, a1, a2 1896# CHECK-INSTR: cv.and.h a0, a1, a2 1897# CHECK-ENCODING: [0x7b,0x85,0xc5,0x68] 1898# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1899 1900cv.and.h s0, s1, s2 1901# CHECK-INSTR: cv.and.h s0, s1, s2 1902# CHECK-ENCODING: [0x7b,0x84,0x24,0x69] 1903# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1904 1905//===----------------------------------------------------------------------===// 1906// cv.and.b 1907//===----------------------------------------------------------------------===// 1908 1909cv.and.b t0, t1, t2 1910# CHECK-INSTR: cv.and.b t0, t1, t2 1911# CHECK-ENCODING: [0xfb,0x12,0x73,0x68] 1912# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1913 1914cv.and.b t3, t4, t5 1915# CHECK-INSTR: cv.and.b t3, t4, t5 1916# CHECK-ENCODING: [0x7b,0x9e,0xee,0x69] 1917# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1918 1919cv.and.b a0, a1, a2 1920# CHECK-INSTR: cv.and.b a0, a1, a2 1921# CHECK-ENCODING: [0x7b,0x95,0xc5,0x68] 1922# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1923 1924cv.and.b s0, s1, s2 1925# CHECK-INSTR: cv.and.b s0, s1, s2 1926# CHECK-ENCODING: [0x7b,0x94,0x24,0x69] 1927# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1928 1929//===----------------------------------------------------------------------===// 1930// cv.and.sc.h 1931//===----------------------------------------------------------------------===// 1932 1933cv.and.sc.h t0, t1, t2 1934# CHECK-INSTR: cv.and.sc.h t0, t1, t2 1935# CHECK-ENCODING: [0xfb,0x42,0x73,0x68] 1936# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1937 1938cv.and.sc.h t3, t4, t5 1939# CHECK-INSTR: cv.and.sc.h t3, t4, t5 1940# CHECK-ENCODING: [0x7b,0xce,0xee,0x69] 1941# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1942 1943cv.and.sc.h a0, a1, a2 1944# CHECK-INSTR: cv.and.sc.h a0, a1, a2 1945# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x68] 1946# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1947 1948cv.and.sc.h s0, s1, s2 1949# CHECK-INSTR: cv.and.sc.h s0, s1, s2 1950# CHECK-ENCODING: [0x7b,0xc4,0x24,0x69] 1951# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1952 1953//===----------------------------------------------------------------------===// 1954// cv.and.sc.b 1955//===----------------------------------------------------------------------===// 1956 1957cv.and.sc.b t0, t1, t2 1958# CHECK-INSTR: cv.and.sc.b t0, t1, t2 1959# CHECK-ENCODING: [0xfb,0x52,0x73,0x68] 1960# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1961 1962cv.and.sc.b t3, t4, t5 1963# CHECK-INSTR: cv.and.sc.b t3, t4, t5 1964# CHECK-ENCODING: [0x7b,0xde,0xee,0x69] 1965# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1966 1967cv.and.sc.b a0, a1, a2 1968# CHECK-INSTR: cv.and.sc.b a0, a1, a2 1969# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x68] 1970# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1971 1972cv.and.sc.b s0, s1, s2 1973# CHECK-INSTR: cv.and.sc.b s0, s1, s2 1974# CHECK-ENCODING: [0x7b,0xd4,0x24,0x69] 1975# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1976 1977//===----------------------------------------------------------------------===// 1978// cv.and.sci.h 1979//===----------------------------------------------------------------------===// 1980 1981cv.and.sci.h t0, t1, 0 1982# CHECK-INSTR: cv.and.sci.h t0, t1, 0 1983# CHECK-ENCODING: [0xfb,0x62,0x03,0x68] 1984# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1985 1986cv.and.sci.h t3, t4, -32 1987# CHECK-INSTR: cv.and.sci.h t3, t4, -32 1988# CHECK-ENCODING: [0x7b,0xee,0x0e,0x69] 1989# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1990 1991cv.and.sci.h a0, a1, 7 1992# CHECK-INSTR: cv.and.sci.h a0, a1, 7 1993# CHECK-ENCODING: [0x7b,0xe5,0x35,0x6a] 1994# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 1995 1996cv.and.sci.h s0, s1, -1 1997# CHECK-INSTR: cv.and.sci.h s0, s1, -1 1998# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x6b] 1999# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2000 2001//===----------------------------------------------------------------------===// 2002// cv.and.sci.b 2003//===----------------------------------------------------------------------===// 2004 2005cv.and.sci.b t0, t1, 0 2006# CHECK-INSTR: cv.and.sci.b t0, t1, 0 2007# CHECK-ENCODING: [0xfb,0x72,0x03,0x68] 2008# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2009 2010cv.and.sci.b t3, t4, -32 2011# CHECK-INSTR: cv.and.sci.b t3, t4, -32 2012# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x69] 2013# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2014 2015cv.and.sci.b a0, a1, 7 2016# CHECK-INSTR: cv.and.sci.b a0, a1, 7 2017# CHECK-ENCODING: [0x7b,0xf5,0x35,0x6a] 2018# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2019 2020cv.and.sci.b s0, s1, -1 2021# CHECK-INSTR: cv.and.sci.b s0, s1, -1 2022# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x6b] 2023# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2024 2025//===----------------------------------------------------------------------===// 2026// cv.abs.h 2027//===----------------------------------------------------------------------===// 2028 2029cv.abs.h t0, t1 2030# CHECK-INSTR: cv.abs.h t0, t1 2031# CHECK-ENCODING: [0xfb,0x02,0x03,0x70] 2032# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2033 2034cv.abs.h t3, t4 2035# CHECK-INSTR: cv.abs.h t3, t4 2036# CHECK-ENCODING: [0x7b,0x8e,0x0e,0x70] 2037# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2038 2039cv.abs.h a0, a1 2040# CHECK-INSTR: cv.abs.h a0, a1 2041# CHECK-ENCODING: [0x7b,0x85,0x05,0x70] 2042# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2043 2044cv.abs.h s0, s1 2045# CHECK-INSTR: cv.abs.h s0, s1 2046# CHECK-ENCODING: [0x7b,0x84,0x04,0x70] 2047# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2048 2049//===----------------------------------------------------------------------===// 2050// cv.abs.b 2051//===----------------------------------------------------------------------===// 2052 2053cv.abs.b t0, t1 2054# CHECK-INSTR: cv.abs.b t0, t1 2055# CHECK-ENCODING: [0xfb,0x12,0x03,0x70] 2056# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2057 2058cv.abs.b t3, t4 2059# CHECK-INSTR: cv.abs.b t3, t4 2060# CHECK-ENCODING: [0x7b,0x9e,0x0e,0x70] 2061# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2062 2063cv.abs.b a0, a1 2064# CHECK-INSTR: cv.abs.b a0, a1 2065# CHECK-ENCODING: [0x7b,0x95,0x05,0x70] 2066# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2067 2068cv.abs.b s0, s1 2069# CHECK-INSTR: cv.abs.b s0, s1 2070# CHECK-ENCODING: [0x7b,0x94,0x04,0x70] 2071# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2072 2073//===----------------------------------------------------------------------===// 2074// cv.dotup.h 2075//===----------------------------------------------------------------------===// 2076 2077cv.dotup.h t0, t1, t2 2078# CHECK-INSTR: cv.dotup.h t0, t1, t2 2079# CHECK-ENCODING: [0xfb,0x02,0x73,0x80] 2080# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2081 2082cv.dotup.h t3, t4, t5 2083# CHECK-INSTR: cv.dotup.h t3, t4, t5 2084# CHECK-ENCODING: [0x7b,0x8e,0xee,0x81] 2085# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2086 2087cv.dotup.h a0, a1, a2 2088# CHECK-INSTR: cv.dotup.h a0, a1, a2 2089# CHECK-ENCODING: [0x7b,0x85,0xc5,0x80] 2090# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2091 2092cv.dotup.h s0, s1, s2 2093# CHECK-INSTR: cv.dotup.h s0, s1, s2 2094# CHECK-ENCODING: [0x7b,0x84,0x24,0x81] 2095# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2096 2097//===----------------------------------------------------------------------===// 2098// cv.dotup.b 2099//===----------------------------------------------------------------------===// 2100 2101cv.dotup.b t0, t1, t2 2102# CHECK-INSTR: cv.dotup.b t0, t1, t2 2103# CHECK-ENCODING: [0xfb,0x12,0x73,0x80] 2104# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2105 2106cv.dotup.b t3, t4, t5 2107# CHECK-INSTR: cv.dotup.b t3, t4, t5 2108# CHECK-ENCODING: [0x7b,0x9e,0xee,0x81] 2109# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2110 2111cv.dotup.b a0, a1, a2 2112# CHECK-INSTR: cv.dotup.b a0, a1, a2 2113# CHECK-ENCODING: [0x7b,0x95,0xc5,0x80] 2114# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2115 2116cv.dotup.b s0, s1, s2 2117# CHECK-INSTR: cv.dotup.b s0, s1, s2 2118# CHECK-ENCODING: [0x7b,0x94,0x24,0x81] 2119# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2120 2121//===----------------------------------------------------------------------===// 2122// cv.dotup.sc.h 2123//===----------------------------------------------------------------------===// 2124 2125cv.dotup.sc.h t0, t1, t2 2126# CHECK-INSTR: cv.dotup.sc.h t0, t1, t2 2127# CHECK-ENCODING: [0xfb,0x42,0x73,0x80] 2128# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2129 2130cv.dotup.sc.h t3, t4, t5 2131# CHECK-INSTR: cv.dotup.sc.h t3, t4, t5 2132# CHECK-ENCODING: [0x7b,0xce,0xee,0x81] 2133# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2134 2135cv.dotup.sc.h a0, a1, a2 2136# CHECK-INSTR: cv.dotup.sc.h a0, a1, a2 2137# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x80] 2138# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2139 2140cv.dotup.sc.h s0, s1, s2 2141# CHECK-INSTR: cv.dotup.sc.h s0, s1, s2 2142# CHECK-ENCODING: [0x7b,0xc4,0x24,0x81] 2143# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2144 2145//===----------------------------------------------------------------------===// 2146// cv.dotup.sc.b 2147//===----------------------------------------------------------------------===// 2148 2149cv.dotup.sc.b t0, t1, t2 2150# CHECK-INSTR: cv.dotup.sc.b t0, t1, t2 2151# CHECK-ENCODING: [0xfb,0x52,0x73,0x80] 2152# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2153 2154cv.dotup.sc.b t3, t4, t5 2155# CHECK-INSTR: cv.dotup.sc.b t3, t4, t5 2156# CHECK-ENCODING: [0x7b,0xde,0xee,0x81] 2157# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2158 2159cv.dotup.sc.b a0, a1, a2 2160# CHECK-INSTR: cv.dotup.sc.b a0, a1, a2 2161# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x80] 2162# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2163 2164cv.dotup.sc.b s0, s1, s2 2165# CHECK-INSTR: cv.dotup.sc.b s0, s1, s2 2166# CHECK-ENCODING: [0x7b,0xd4,0x24,0x81] 2167# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2168 2169//===----------------------------------------------------------------------===// 2170// cv.dotup.sci.h 2171//===----------------------------------------------------------------------===// 2172 2173cv.dotup.sci.h t0, t1, 0 2174# CHECK-INSTR: cv.dotup.sci.h t0, t1, 0 2175# CHECK-ENCODING: [0xfb,0x62,0x03,0x80] 2176# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2177 2178cv.dotup.sci.h t3, t4, 32 2179# CHECK-INSTR: cv.dotup.sci.h t3, t4, 32 2180# CHECK-ENCODING: [0x7b,0xee,0x0e,0x81] 2181# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2182 2183cv.dotup.sci.h a0, a1, 7 2184# CHECK-INSTR: cv.dotup.sci.h a0, a1, 7 2185# CHECK-ENCODING: [0x7b,0xe5,0x35,0x82] 2186# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2187 2188cv.dotup.sci.h s0, s1, 63 2189# CHECK-INSTR: cv.dotup.sci.h s0, s1, 63 2190# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x83] 2191# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2192 2193//===----------------------------------------------------------------------===// 2194// cv.dotup.sci.b 2195//===----------------------------------------------------------------------===// 2196 2197cv.dotup.sci.b t0, t1, 0 2198# CHECK-INSTR: cv.dotup.sci.b t0, t1, 0 2199# CHECK-ENCODING: [0xfb,0x72,0x03,0x80] 2200# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2201 2202cv.dotup.sci.b t3, t4, 32 2203# CHECK-INSTR: cv.dotup.sci.b t3, t4, 32 2204# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x81] 2205# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2206 2207cv.dotup.sci.b a0, a1, 7 2208# CHECK-INSTR: cv.dotup.sci.b a0, a1, 7 2209# CHECK-ENCODING: [0x7b,0xf5,0x35,0x82] 2210# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2211 2212cv.dotup.sci.b s0, s1, 63 2213# CHECK-INSTR: cv.dotup.sci.b s0, s1, 63 2214# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x83] 2215# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2216 2217//===----------------------------------------------------------------------===// 2218// cv.dotusp.h 2219//===----------------------------------------------------------------------===// 2220 2221cv.dotusp.h t0, t1, t2 2222# CHECK-INSTR: cv.dotusp.h t0, t1, t2 2223# CHECK-ENCODING: [0xfb,0x02,0x73,0x88] 2224# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2225 2226cv.dotusp.h t3, t4, t5 2227# CHECK-INSTR: cv.dotusp.h t3, t4, t5 2228# CHECK-ENCODING: [0x7b,0x8e,0xee,0x89] 2229# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2230 2231cv.dotusp.h a0, a1, a2 2232# CHECK-INSTR: cv.dotusp.h a0, a1, a2 2233# CHECK-ENCODING: [0x7b,0x85,0xc5,0x88] 2234# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2235 2236cv.dotusp.h s0, s1, s2 2237# CHECK-INSTR: cv.dotusp.h s0, s1, s2 2238# CHECK-ENCODING: [0x7b,0x84,0x24,0x89] 2239# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2240 2241//===----------------------------------------------------------------------===// 2242// cv.dotusp.b 2243//===----------------------------------------------------------------------===// 2244 2245cv.dotusp.b t0, t1, t2 2246# CHECK-INSTR: cv.dotusp.b t0, t1, t2 2247# CHECK-ENCODING: [0xfb,0x12,0x73,0x88] 2248# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2249 2250cv.dotusp.b t3, t4, t5 2251# CHECK-INSTR: cv.dotusp.b t3, t4, t5 2252# CHECK-ENCODING: [0x7b,0x9e,0xee,0x89] 2253# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2254 2255cv.dotusp.b a0, a1, a2 2256# CHECK-INSTR: cv.dotusp.b a0, a1, a2 2257# CHECK-ENCODING: [0x7b,0x95,0xc5,0x88] 2258# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2259 2260cv.dotusp.b s0, s1, s2 2261# CHECK-INSTR: cv.dotusp.b s0, s1, s2 2262# CHECK-ENCODING: [0x7b,0x94,0x24,0x89] 2263# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2264 2265//===----------------------------------------------------------------------===// 2266// cv.dotusp.sc.h 2267//===----------------------------------------------------------------------===// 2268 2269cv.dotusp.sc.h t0, t1, t2 2270# CHECK-INSTR: cv.dotusp.sc.h t0, t1, t2 2271# CHECK-ENCODING: [0xfb,0x42,0x73,0x88] 2272# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2273 2274cv.dotusp.sc.h t3, t4, t5 2275# CHECK-INSTR: cv.dotusp.sc.h t3, t4, t5 2276# CHECK-ENCODING: [0x7b,0xce,0xee,0x89] 2277# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2278 2279cv.dotusp.sc.h a0, a1, a2 2280# CHECK-INSTR: cv.dotusp.sc.h a0, a1, a2 2281# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x88] 2282# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2283 2284cv.dotusp.sc.h s0, s1, s2 2285# CHECK-INSTR: cv.dotusp.sc.h s0, s1, s2 2286# CHECK-ENCODING: [0x7b,0xc4,0x24,0x89] 2287# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2288 2289//===----------------------------------------------------------------------===// 2290// cv.dotusp.sc.b 2291//===----------------------------------------------------------------------===// 2292 2293cv.dotusp.sc.b t0, t1, t2 2294# CHECK-INSTR: cv.dotusp.sc.b t0, t1, t2 2295# CHECK-ENCODING: [0xfb,0x52,0x73,0x88] 2296# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2297 2298cv.dotusp.sc.b t3, t4, t5 2299# CHECK-INSTR: cv.dotusp.sc.b t3, t4, t5 2300# CHECK-ENCODING: [0x7b,0xde,0xee,0x89] 2301# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2302 2303cv.dotusp.sc.b a0, a1, a2 2304# CHECK-INSTR: cv.dotusp.sc.b a0, a1, a2 2305# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x88] 2306# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2307 2308cv.dotusp.sc.b s0, s1, s2 2309# CHECK-INSTR: cv.dotusp.sc.b s0, s1, s2 2310# CHECK-ENCODING: [0x7b,0xd4,0x24,0x89] 2311# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2312 2313//===----------------------------------------------------------------------===// 2314// cv.dotusp.sci.h 2315//===----------------------------------------------------------------------===// 2316 2317cv.dotusp.sci.h t0, t1, 0 2318# CHECK-INSTR: cv.dotusp.sci.h t0, t1, 0 2319# CHECK-ENCODING: [0xfb,0x62,0x03,0x88] 2320# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2321 2322cv.dotusp.sci.h t3, t4, -32 2323# CHECK-INSTR: cv.dotusp.sci.h t3, t4, -32 2324# CHECK-ENCODING: [0x7b,0xee,0x0e,0x89] 2325# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2326 2327cv.dotusp.sci.h a0, a1, 7 2328# CHECK-INSTR: cv.dotusp.sci.h a0, a1, 7 2329# CHECK-ENCODING: [0x7b,0xe5,0x35,0x8a] 2330# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2331 2332cv.dotusp.sci.h s0, s1, -1 2333# CHECK-INSTR: cv.dotusp.sci.h s0, s1, -1 2334# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x8b] 2335# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2336 2337//===----------------------------------------------------------------------===// 2338// cv.dotusp.sci.b 2339//===----------------------------------------------------------------------===// 2340 2341cv.dotusp.sci.b t0, t1, 0 2342# CHECK-INSTR: cv.dotusp.sci.b t0, t1, 0 2343# CHECK-ENCODING: [0xfb,0x72,0x03,0x88] 2344# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2345 2346cv.dotusp.sci.b t3, t4, -32 2347# CHECK-INSTR: cv.dotusp.sci.b t3, t4, -32 2348# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x89] 2349# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2350 2351cv.dotusp.sci.b a0, a1, 7 2352# CHECK-INSTR: cv.dotusp.sci.b a0, a1, 7 2353# CHECK-ENCODING: [0x7b,0xf5,0x35,0x8a] 2354# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2355 2356cv.dotusp.sci.b s0, s1, -1 2357# CHECK-INSTR: cv.dotusp.sci.b s0, s1, -1 2358# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x8b] 2359# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2360 2361//===----------------------------------------------------------------------===// 2362// cv.dotsp.h 2363//===----------------------------------------------------------------------===// 2364 2365cv.dotsp.h t0, t1, t2 2366# CHECK-INSTR: cv.dotsp.h t0, t1, t2 2367# CHECK-ENCODING: [0xfb,0x02,0x73,0x90] 2368# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2369 2370cv.dotsp.h t3, t4, t5 2371# CHECK-INSTR: cv.dotsp.h t3, t4, t5 2372# CHECK-ENCODING: [0x7b,0x8e,0xee,0x91] 2373# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2374 2375cv.dotsp.h a0, a1, a2 2376# CHECK-INSTR: cv.dotsp.h a0, a1, a2 2377# CHECK-ENCODING: [0x7b,0x85,0xc5,0x90] 2378# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2379 2380cv.dotsp.h s0, s1, s2 2381# CHECK-INSTR: cv.dotsp.h s0, s1, s2 2382# CHECK-ENCODING: [0x7b,0x84,0x24,0x91] 2383# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2384 2385//===----------------------------------------------------------------------===// 2386// cv.dotsp.b 2387//===----------------------------------------------------------------------===// 2388 2389cv.dotsp.b t0, t1, t2 2390# CHECK-INSTR: cv.dotsp.b t0, t1, t2 2391# CHECK-ENCODING: [0xfb,0x12,0x73,0x90] 2392# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2393 2394cv.dotsp.b t3, t4, t5 2395# CHECK-INSTR: cv.dotsp.b t3, t4, t5 2396# CHECK-ENCODING: [0x7b,0x9e,0xee,0x91] 2397# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2398 2399cv.dotsp.b a0, a1, a2 2400# CHECK-INSTR: cv.dotsp.b a0, a1, a2 2401# CHECK-ENCODING: [0x7b,0x95,0xc5,0x90] 2402# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2403 2404cv.dotsp.b s0, s1, s2 2405# CHECK-INSTR: cv.dotsp.b s0, s1, s2 2406# CHECK-ENCODING: [0x7b,0x94,0x24,0x91] 2407# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2408 2409//===----------------------------------------------------------------------===// 2410// cv.dotsp.sc.h 2411//===----------------------------------------------------------------------===// 2412 2413cv.dotsp.sc.h t0, t1, t2 2414# CHECK-INSTR: cv.dotsp.sc.h t0, t1, t2 2415# CHECK-ENCODING: [0xfb,0x42,0x73,0x90] 2416# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2417 2418cv.dotsp.sc.h t3, t4, t5 2419# CHECK-INSTR: cv.dotsp.sc.h t3, t4, t5 2420# CHECK-ENCODING: [0x7b,0xce,0xee,0x91] 2421# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2422 2423cv.dotsp.sc.h a0, a1, a2 2424# CHECK-INSTR: cv.dotsp.sc.h a0, a1, a2 2425# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x90] 2426# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2427 2428cv.dotsp.sc.h s0, s1, s2 2429# CHECK-INSTR: cv.dotsp.sc.h s0, s1, s2 2430# CHECK-ENCODING: [0x7b,0xc4,0x24,0x91] 2431# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2432 2433//===----------------------------------------------------------------------===// 2434// cv.dotsp.sc.b 2435//===----------------------------------------------------------------------===// 2436 2437cv.dotsp.sc.b t0, t1, t2 2438# CHECK-INSTR: cv.dotsp.sc.b t0, t1, t2 2439# CHECK-ENCODING: [0xfb,0x52,0x73,0x90] 2440# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2441 2442cv.dotsp.sc.b t3, t4, t5 2443# CHECK-INSTR: cv.dotsp.sc.b t3, t4, t5 2444# CHECK-ENCODING: [0x7b,0xde,0xee,0x91] 2445# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2446 2447cv.dotsp.sc.b a0, a1, a2 2448# CHECK-INSTR: cv.dotsp.sc.b a0, a1, a2 2449# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x90] 2450# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2451 2452cv.dotsp.sc.b s0, s1, s2 2453# CHECK-INSTR: cv.dotsp.sc.b s0, s1, s2 2454# CHECK-ENCODING: [0x7b,0xd4,0x24,0x91] 2455# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2456 2457//===----------------------------------------------------------------------===// 2458// cv.dotsp.sci.h 2459//===----------------------------------------------------------------------===// 2460 2461cv.dotsp.sci.h t0, t1, 0 2462# CHECK-INSTR: cv.dotsp.sci.h t0, t1, 0 2463# CHECK-ENCODING: [0xfb,0x62,0x03,0x90] 2464# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2465 2466cv.dotsp.sci.h t3, t4, -32 2467# CHECK-INSTR: cv.dotsp.sci.h t3, t4, -32 2468# CHECK-ENCODING: [0x7b,0xee,0x0e,0x91] 2469# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2470 2471cv.dotsp.sci.h a0, a1, 7 2472# CHECK-INSTR: cv.dotsp.sci.h a0, a1, 7 2473# CHECK-ENCODING: [0x7b,0xe5,0x35,0x92] 2474# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2475 2476cv.dotsp.sci.h s0, s1, -1 2477# CHECK-INSTR: cv.dotsp.sci.h s0, s1, -1 2478# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x93] 2479# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2480 2481//===----------------------------------------------------------------------===// 2482// cv.dotsp.sci.b 2483//===----------------------------------------------------------------------===// 2484 2485cv.dotsp.sci.b t0, t1, 0 2486# CHECK-INSTR: cv.dotsp.sci.b t0, t1, 0 2487# CHECK-ENCODING: [0xfb,0x72,0x03,0x90] 2488# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2489 2490cv.dotsp.sci.b t3, t4, -32 2491# CHECK-INSTR: cv.dotsp.sci.b t3, t4, -32 2492# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x91] 2493# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2494 2495cv.dotsp.sci.b a0, a1, 7 2496# CHECK-INSTR: cv.dotsp.sci.b a0, a1, 7 2497# CHECK-ENCODING: [0x7b,0xf5,0x35,0x92] 2498# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2499 2500cv.dotsp.sci.b s0, s1, -1 2501# CHECK-INSTR: cv.dotsp.sci.b s0, s1, -1 2502# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x93] 2503# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2504 2505//===----------------------------------------------------------------------===// 2506// cv.sdotup.h 2507//===----------------------------------------------------------------------===// 2508 2509cv.sdotup.h t0, t1, t2 2510# CHECK-INSTR: cv.sdotup.h t0, t1, t2 2511# CHECK-ENCODING: [0xfb,0x02,0x73,0x98] 2512# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2513 2514cv.sdotup.h t3, t4, t5 2515# CHECK-INSTR: cv.sdotup.h t3, t4, t5 2516# CHECK-ENCODING: [0x7b,0x8e,0xee,0x99] 2517# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2518 2519cv.sdotup.h a0, a1, a2 2520# CHECK-INSTR: cv.sdotup.h a0, a1, a2 2521# CHECK-ENCODING: [0x7b,0x85,0xc5,0x98] 2522# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2523 2524cv.sdotup.h s0, s1, s2 2525# CHECK-INSTR: cv.sdotup.h s0, s1, s2 2526# CHECK-ENCODING: [0x7b,0x84,0x24,0x99] 2527# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2528 2529//===----------------------------------------------------------------------===// 2530// cv.sdotup.b 2531//===----------------------------------------------------------------------===// 2532 2533cv.sdotup.b t0, t1, t2 2534# CHECK-INSTR: cv.sdotup.b t0, t1, t2 2535# CHECK-ENCODING: [0xfb,0x12,0x73,0x98] 2536# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2537 2538cv.sdotup.b t3, t4, t5 2539# CHECK-INSTR: cv.sdotup.b t3, t4, t5 2540# CHECK-ENCODING: [0x7b,0x9e,0xee,0x99] 2541# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2542 2543cv.sdotup.b a0, a1, a2 2544# CHECK-INSTR: cv.sdotup.b a0, a1, a2 2545# CHECK-ENCODING: [0x7b,0x95,0xc5,0x98] 2546# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2547 2548cv.sdotup.b s0, s1, s2 2549# CHECK-INSTR: cv.sdotup.b s0, s1, s2 2550# CHECK-ENCODING: [0x7b,0x94,0x24,0x99] 2551# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2552 2553//===----------------------------------------------------------------------===// 2554// cv.sdotup.sc.h 2555//===----------------------------------------------------------------------===// 2556 2557cv.sdotup.sc.h t0, t1, t2 2558# CHECK-INSTR: cv.sdotup.sc.h t0, t1, t2 2559# CHECK-ENCODING: [0xfb,0x42,0x73,0x98] 2560# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2561 2562cv.sdotup.sc.h t3, t4, t5 2563# CHECK-INSTR: cv.sdotup.sc.h t3, t4, t5 2564# CHECK-ENCODING: [0x7b,0xce,0xee,0x99] 2565# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2566 2567cv.sdotup.sc.h a0, a1, a2 2568# CHECK-INSTR: cv.sdotup.sc.h a0, a1, a2 2569# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x98] 2570# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2571 2572cv.sdotup.sc.h s0, s1, s2 2573# CHECK-INSTR: cv.sdotup.sc.h s0, s1, s2 2574# CHECK-ENCODING: [0x7b,0xc4,0x24,0x99] 2575# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2576 2577//===----------------------------------------------------------------------===// 2578// cv.sdotup.sc.b 2579//===----------------------------------------------------------------------===// 2580 2581cv.sdotup.sc.b t0, t1, t2 2582# CHECK-INSTR: cv.sdotup.sc.b t0, t1, t2 2583# CHECK-ENCODING: [0xfb,0x52,0x73,0x98] 2584# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2585 2586cv.sdotup.sc.b t3, t4, t5 2587# CHECK-INSTR: cv.sdotup.sc.b t3, t4, t5 2588# CHECK-ENCODING: [0x7b,0xde,0xee,0x99] 2589# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2590 2591cv.sdotup.sc.b a0, a1, a2 2592# CHECK-INSTR: cv.sdotup.sc.b a0, a1, a2 2593# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x98] 2594# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2595 2596cv.sdotup.sc.b s0, s1, s2 2597# CHECK-INSTR: cv.sdotup.sc.b s0, s1, s2 2598# CHECK-ENCODING: [0x7b,0xd4,0x24,0x99] 2599# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2600 2601//===----------------------------------------------------------------------===// 2602// cv.sdotup.sci.h 2603//===----------------------------------------------------------------------===// 2604 2605cv.sdotup.sci.h t0, t1, 0 2606# CHECK-INSTR: cv.sdotup.sci.h t0, t1, 0 2607# CHECK-ENCODING: [0xfb,0x62,0x03,0x98] 2608# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2609 2610cv.sdotup.sci.h t3, t4, 32 2611# CHECK-INSTR: cv.sdotup.sci.h t3, t4, 32 2612# CHECK-ENCODING: [0x7b,0xee,0x0e,0x99] 2613# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2614 2615cv.sdotup.sci.h a0, a1, 7 2616# CHECK-INSTR: cv.sdotup.sci.h a0, a1, 7 2617# CHECK-ENCODING: [0x7b,0xe5,0x35,0x9a] 2618# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2619 2620cv.sdotup.sci.h s0, s1, 63 2621# CHECK-INSTR: cv.sdotup.sci.h s0, s1, 63 2622# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x9b] 2623# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2624 2625//===----------------------------------------------------------------------===// 2626// cv.sdotup.sci.b 2627//===----------------------------------------------------------------------===// 2628 2629cv.sdotup.sci.b t0, t1, 0 2630# CHECK-INSTR: cv.sdotup.sci.b t0, t1, 0 2631# CHECK-ENCODING: [0xfb,0x72,0x03,0x98] 2632# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2633 2634cv.sdotup.sci.b t3, t4, 32 2635# CHECK-INSTR: cv.sdotup.sci.b t3, t4, 32 2636# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x99] 2637# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2638 2639cv.sdotup.sci.b a0, a1, 7 2640# CHECK-INSTR: cv.sdotup.sci.b a0, a1, 7 2641# CHECK-ENCODING: [0x7b,0xf5,0x35,0x9a] 2642# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2643 2644cv.sdotup.sci.b s0, s1, 63 2645# CHECK-INSTR: cv.sdotup.sci.b s0, s1, 63 2646# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x9b] 2647# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2648 2649//===----------------------------------------------------------------------===// 2650// cv.sdotusp.h 2651//===----------------------------------------------------------------------===// 2652 2653cv.sdotusp.h t0, t1, t2 2654# CHECK-INSTR: cv.sdotusp.h t0, t1, t2 2655# CHECK-ENCODING: [0xfb,0x02,0x73,0xa0] 2656# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2657 2658cv.sdotusp.h t3, t4, t5 2659# CHECK-INSTR: cv.sdotusp.h t3, t4, t5 2660# CHECK-ENCODING: [0x7b,0x8e,0xee,0xa1] 2661# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2662 2663cv.sdotusp.h a0, a1, a2 2664# CHECK-INSTR: cv.sdotusp.h a0, a1, a2 2665# CHECK-ENCODING: [0x7b,0x85,0xc5,0xa0] 2666# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2667 2668cv.sdotusp.h s0, s1, s2 2669# CHECK-INSTR: cv.sdotusp.h s0, s1, s2 2670# CHECK-ENCODING: [0x7b,0x84,0x24,0xa1] 2671# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2672 2673//===----------------------------------------------------------------------===// 2674// cv.sdotusp.b 2675//===----------------------------------------------------------------------===// 2676 2677cv.sdotusp.b t0, t1, t2 2678# CHECK-INSTR: cv.sdotusp.b t0, t1, t2 2679# CHECK-ENCODING: [0xfb,0x12,0x73,0xa0] 2680# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2681 2682cv.sdotusp.b t3, t4, t5 2683# CHECK-INSTR: cv.sdotusp.b t3, t4, t5 2684# CHECK-ENCODING: [0x7b,0x9e,0xee,0xa1] 2685# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2686 2687cv.sdotusp.b a0, a1, a2 2688# CHECK-INSTR: cv.sdotusp.b a0, a1, a2 2689# CHECK-ENCODING: [0x7b,0x95,0xc5,0xa0] 2690# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2691 2692cv.sdotusp.b s0, s1, s2 2693# CHECK-INSTR: cv.sdotusp.b s0, s1, s2 2694# CHECK-ENCODING: [0x7b,0x94,0x24,0xa1] 2695# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2696 2697//===----------------------------------------------------------------------===// 2698// cv.sdotusp.sc.h 2699//===----------------------------------------------------------------------===// 2700 2701cv.sdotusp.sc.h t0, t1, t2 2702# CHECK-INSTR: cv.sdotusp.sc.h t0, t1, t2 2703# CHECK-ENCODING: [0xfb,0x42,0x73,0xa0] 2704# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2705 2706cv.sdotusp.sc.h t3, t4, t5 2707# CHECK-INSTR: cv.sdotusp.sc.h t3, t4, t5 2708# CHECK-ENCODING: [0x7b,0xce,0xee,0xa1] 2709# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2710 2711cv.sdotusp.sc.h a0, a1, a2 2712# CHECK-INSTR: cv.sdotusp.sc.h a0, a1, a2 2713# CHECK-ENCODING: [0x7b,0xc5,0xc5,0xa0] 2714# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2715 2716cv.sdotusp.sc.h s0, s1, s2 2717# CHECK-INSTR: cv.sdotusp.sc.h s0, s1, s2 2718# CHECK-ENCODING: [0x7b,0xc4,0x24,0xa1] 2719# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2720 2721//===----------------------------------------------------------------------===// 2722// cv.sdotusp.sc.b 2723//===----------------------------------------------------------------------===// 2724 2725cv.sdotusp.sc.b t0, t1, t2 2726# CHECK-INSTR: cv.sdotusp.sc.b t0, t1, t2 2727# CHECK-ENCODING: [0xfb,0x52,0x73,0xa0] 2728# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2729 2730cv.sdotusp.sc.b t3, t4, t5 2731# CHECK-INSTR: cv.sdotusp.sc.b t3, t4, t5 2732# CHECK-ENCODING: [0x7b,0xde,0xee,0xa1] 2733# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2734 2735cv.sdotusp.sc.b a0, a1, a2 2736# CHECK-INSTR: cv.sdotusp.sc.b a0, a1, a2 2737# CHECK-ENCODING: [0x7b,0xd5,0xc5,0xa0] 2738# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2739 2740cv.sdotusp.sc.b s0, s1, s2 2741# CHECK-INSTR: cv.sdotusp.sc.b s0, s1, s2 2742# CHECK-ENCODING: [0x7b,0xd4,0x24,0xa1] 2743# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2744 2745//===----------------------------------------------------------------------===// 2746// cv.sdotusp.sci.h 2747//===----------------------------------------------------------------------===// 2748 2749cv.sdotusp.sci.h t0, t1, 0 2750# CHECK-INSTR: cv.sdotusp.sci.h t0, t1, 0 2751# CHECK-ENCODING: [0xfb,0x62,0x03,0xa0] 2752# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2753 2754cv.sdotusp.sci.h t3, t4, -32 2755# CHECK-INSTR: cv.sdotusp.sci.h t3, t4, -32 2756# CHECK-ENCODING: [0x7b,0xee,0x0e,0xa1] 2757# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2758 2759cv.sdotusp.sci.h a0, a1, 7 2760# CHECK-INSTR: cv.sdotusp.sci.h a0, a1, 7 2761# CHECK-ENCODING: [0x7b,0xe5,0x35,0xa2] 2762# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2763 2764cv.sdotusp.sci.h s0, s1, -1 2765# CHECK-INSTR: cv.sdotusp.sci.h s0, s1, -1 2766# CHECK-ENCODING: [0x7b,0xe4,0xf4,0xa3] 2767# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2768 2769//===----------------------------------------------------------------------===// 2770// cv.sdotusp.sci.b 2771//===----------------------------------------------------------------------===// 2772 2773cv.sdotusp.sci.b t0, t1, 0 2774# CHECK-INSTR: cv.sdotusp.sci.b t0, t1, 0 2775# CHECK-ENCODING: [0xfb,0x72,0x03,0xa0] 2776# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2777 2778cv.sdotusp.sci.b t3, t4, -32 2779# CHECK-INSTR: cv.sdotusp.sci.b t3, t4, -32 2780# CHECK-ENCODING: [0x7b,0xfe,0x0e,0xa1] 2781# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2782 2783cv.sdotusp.sci.b a0, a1, 7 2784# CHECK-INSTR: cv.sdotusp.sci.b a0, a1, 7 2785# CHECK-ENCODING: [0x7b,0xf5,0x35,0xa2] 2786# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2787 2788cv.sdotusp.sci.b s0, s1, -1 2789# CHECK-INSTR: cv.sdotusp.sci.b s0, s1, -1 2790# CHECK-ENCODING: [0x7b,0xf4,0xf4,0xa3] 2791# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2792 2793//===----------------------------------------------------------------------===// 2794// cv.sdotsp.h 2795//===----------------------------------------------------------------------===// 2796 2797cv.sdotsp.h t0, t1, t2 2798# CHECK-INSTR: cv.sdotsp.h t0, t1, t2 2799# CHECK-ENCODING: [0xfb,0x02,0x73,0xa8] 2800# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2801 2802cv.sdotsp.h t3, t4, t5 2803# CHECK-INSTR: cv.sdotsp.h t3, t4, t5 2804# CHECK-ENCODING: [0x7b,0x8e,0xee,0xa9] 2805# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2806 2807cv.sdotsp.h a0, a1, a2 2808# CHECK-INSTR: cv.sdotsp.h a0, a1, a2 2809# CHECK-ENCODING: [0x7b,0x85,0xc5,0xa8] 2810# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2811 2812cv.sdotsp.h s0, s1, s2 2813# CHECK-INSTR: cv.sdotsp.h s0, s1, s2 2814# CHECK-ENCODING: [0x7b,0x84,0x24,0xa9] 2815# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2816 2817//===----------------------------------------------------------------------===// 2818// cv.sdotsp.b 2819//===----------------------------------------------------------------------===// 2820 2821cv.sdotsp.b t0, t1, t2 2822# CHECK-INSTR: cv.sdotsp.b t0, t1, t2 2823# CHECK-ENCODING: [0xfb,0x12,0x73,0xa8] 2824# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2825 2826cv.sdotsp.b t3, t4, t5 2827# CHECK-INSTR: cv.sdotsp.b t3, t4, t5 2828# CHECK-ENCODING: [0x7b,0x9e,0xee,0xa9] 2829# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2830 2831cv.sdotsp.b a0, a1, a2 2832# CHECK-INSTR: cv.sdotsp.b a0, a1, a2 2833# CHECK-ENCODING: [0x7b,0x95,0xc5,0xa8] 2834# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2835 2836cv.sdotsp.b s0, s1, s2 2837# CHECK-INSTR: cv.sdotsp.b s0, s1, s2 2838# CHECK-ENCODING: [0x7b,0x94,0x24,0xa9] 2839# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2840 2841//===----------------------------------------------------------------------===// 2842// cv.sdotsp.sc.h 2843//===----------------------------------------------------------------------===// 2844 2845cv.sdotsp.sc.h t0, t1, t2 2846# CHECK-INSTR: cv.sdotsp.sc.h t0, t1, t2 2847# CHECK-ENCODING: [0xfb,0x42,0x73,0xa8] 2848# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2849 2850cv.sdotsp.sc.h t3, t4, t5 2851# CHECK-INSTR: cv.sdotsp.sc.h t3, t4, t5 2852# CHECK-ENCODING: [0x7b,0xce,0xee,0xa9] 2853# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2854 2855cv.sdotsp.sc.h a0, a1, a2 2856# CHECK-INSTR: cv.sdotsp.sc.h a0, a1, a2 2857# CHECK-ENCODING: [0x7b,0xc5,0xc5,0xa8] 2858# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2859 2860cv.sdotsp.sc.h s0, s1, s2 2861# CHECK-INSTR: cv.sdotsp.sc.h s0, s1, s2 2862# CHECK-ENCODING: [0x7b,0xc4,0x24,0xa9] 2863# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2864 2865//===----------------------------------------------------------------------===// 2866// cv.sdotsp.sc.b 2867//===----------------------------------------------------------------------===// 2868 2869cv.sdotsp.sc.b t0, t1, t2 2870# CHECK-INSTR: cv.sdotsp.sc.b t0, t1, t2 2871# CHECK-ENCODING: [0xfb,0x52,0x73,0xa8] 2872# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2873 2874cv.sdotsp.sc.b t3, t4, t5 2875# CHECK-INSTR: cv.sdotsp.sc.b t3, t4, t5 2876# CHECK-ENCODING: [0x7b,0xde,0xee,0xa9] 2877# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2878 2879cv.sdotsp.sc.b a0, a1, a2 2880# CHECK-INSTR: cv.sdotsp.sc.b a0, a1, a2 2881# CHECK-ENCODING: [0x7b,0xd5,0xc5,0xa8] 2882# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2883 2884cv.sdotsp.sc.b s0, s1, s2 2885# CHECK-INSTR: cv.sdotsp.sc.b s0, s1, s2 2886# CHECK-ENCODING: [0x7b,0xd4,0x24,0xa9] 2887# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2888 2889//===----------------------------------------------------------------------===// 2890// cv.sdotsp.sci.h 2891//===----------------------------------------------------------------------===// 2892 2893cv.sdotsp.sci.h t0, t1, 0 2894# CHECK-INSTR: cv.sdotsp.sci.h t0, t1, 0 2895# CHECK-ENCODING: [0xfb,0x62,0x03,0xa8] 2896# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2897 2898cv.sdotsp.sci.h t3, t4, -32 2899# CHECK-INSTR: cv.sdotsp.sci.h t3, t4, -32 2900# CHECK-ENCODING: [0x7b,0xee,0x0e,0xa9] 2901# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2902 2903cv.sdotsp.sci.h a0, a1, 7 2904# CHECK-INSTR: cv.sdotsp.sci.h a0, a1, 7 2905# CHECK-ENCODING: [0x7b,0xe5,0x35,0xaa] 2906# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2907 2908cv.sdotsp.sci.h s0, s1, -1 2909# CHECK-INSTR: cv.sdotsp.sci.h s0, s1, -1 2910# CHECK-ENCODING: [0x7b,0xe4,0xf4,0xab] 2911# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2912 2913//===----------------------------------------------------------------------===// 2914// cv.sdotsp.sci.b 2915//===----------------------------------------------------------------------===// 2916 2917cv.sdotsp.sci.b t0, t1, 0 2918# CHECK-INSTR: cv.sdotsp.sci.b t0, t1, 0 2919# CHECK-ENCODING: [0xfb,0x72,0x03,0xa8] 2920# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2921 2922cv.sdotsp.sci.b t3, t4, -32 2923# CHECK-INSTR: cv.sdotsp.sci.b t3, t4, -32 2924# CHECK-ENCODING: [0x7b,0xfe,0x0e,0xa9] 2925# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2926 2927cv.sdotsp.sci.b a0, a1, 7 2928# CHECK-INSTR: cv.sdotsp.sci.b a0, a1, 7 2929# CHECK-ENCODING: [0x7b,0xf5,0x35,0xaa] 2930# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2931 2932cv.sdotsp.sci.b s0, s1, -1 2933# CHECK-INSTR: cv.sdotsp.sci.b s0, s1, -1 2934# CHECK-ENCODING: [0x7b,0xf4,0xf4,0xab] 2935# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2936 2937//===----------------------------------------------------------------------===// 2938// cv.extract.h 2939//===----------------------------------------------------------------------===// 2940 2941cv.extract.h t0, t1, 0 2942# CHECK-INSTR: cv.extract.h t0, t1, 0 2943# CHECK-ENCODING: [0xfb,0x02,0x03,0xb8] 2944# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2945 2946cv.extract.h t3, t4, 32 2947# CHECK-INSTR: cv.extract.h t3, t4, 32 2948# CHECK-ENCODING: [0x7b,0x8e,0x0e,0xb9] 2949# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2950 2951cv.extract.h a0, a1, 7 2952# CHECK-INSTR: cv.extract.h a0, a1, 7 2953# CHECK-ENCODING: [0x7b,0x85,0x35,0xba] 2954# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2955 2956cv.extract.h s0, s1, 63 2957# CHECK-INSTR: cv.extract.h s0, s1, 63 2958# CHECK-ENCODING: [0x7b,0x84,0xf4,0xbb] 2959# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2960 2961//===----------------------------------------------------------------------===// 2962// cv.extract.b 2963//===----------------------------------------------------------------------===// 2964 2965cv.extract.b t0, t1, 0 2966# CHECK-INSTR: cv.extract.b t0, t1, 0 2967# CHECK-ENCODING: [0xfb,0x12,0x03,0xb8] 2968# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2969 2970cv.extract.b t3, t4, 32 2971# CHECK-INSTR: cv.extract.b t3, t4, 32 2972# CHECK-ENCODING: [0x7b,0x9e,0x0e,0xb9] 2973# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2974 2975cv.extract.b a0, a1, 7 2976# CHECK-INSTR: cv.extract.b a0, a1, 7 2977# CHECK-ENCODING: [0x7b,0x95,0x35,0xba] 2978# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2979 2980cv.extract.b s0, s1, 63 2981# CHECK-INSTR: cv.extract.b s0, s1, 63 2982# CHECK-ENCODING: [0x7b,0x94,0xf4,0xbb] 2983# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2984 2985//===----------------------------------------------------------------------===// 2986// cv.extractu.h 2987//===----------------------------------------------------------------------===// 2988 2989cv.extractu.h t0, t1, 0 2990# CHECK-INSTR: cv.extractu.h t0, t1, 0 2991# CHECK-ENCODING: [0xfb,0x22,0x03,0xb8] 2992# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2993 2994cv.extractu.h t3, t4, 32 2995# CHECK-INSTR: cv.extractu.h t3, t4, 32 2996# CHECK-ENCODING: [0x7b,0xae,0x0e,0xb9] 2997# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 2998 2999cv.extractu.h a0, a1, 7 3000# CHECK-INSTR: cv.extractu.h a0, a1, 7 3001# CHECK-ENCODING: [0x7b,0xa5,0x35,0xba] 3002# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3003 3004cv.extractu.h s0, s1, 63 3005# CHECK-INSTR: cv.extractu.h s0, s1, 63 3006# CHECK-ENCODING: [0x7b,0xa4,0xf4,0xbb] 3007# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3008 3009//===----------------------------------------------------------------------===// 3010// cv.extractu.b 3011//===----------------------------------------------------------------------===// 3012 3013cv.extractu.b t0, t1, 0 3014# CHECK-INSTR: cv.extractu.b t0, t1, 0 3015# CHECK-ENCODING: [0xfb,0x32,0x03,0xb8] 3016# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3017 3018cv.extractu.b t3, t4, 32 3019# CHECK-INSTR: cv.extractu.b t3, t4, 32 3020# CHECK-ENCODING: [0x7b,0xbe,0x0e,0xb9] 3021# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3022 3023cv.extractu.b a0, a1, 7 3024# CHECK-INSTR: cv.extractu.b a0, a1, 7 3025# CHECK-ENCODING: [0x7b,0xb5,0x35,0xba] 3026# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3027 3028cv.extractu.b s0, s1, 63 3029# CHECK-INSTR: cv.extractu.b s0, s1, 63 3030# CHECK-ENCODING: [0x7b,0xb4,0xf4,0xbb] 3031# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3032 3033//===----------------------------------------------------------------------===// 3034// cv.insert.h 3035//===----------------------------------------------------------------------===// 3036 3037cv.insert.h t0, t1, 0 3038# CHECK-INSTR: cv.insert.h t0, t1, 0 3039# CHECK-ENCODING: [0xfb,0x42,0x03,0xb8] 3040# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3041 3042cv.insert.h t3, t4, 32 3043# CHECK-INSTR: cv.insert.h t3, t4, 32 3044# CHECK-ENCODING: [0x7b,0xce,0x0e,0xb9] 3045# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3046 3047cv.insert.h a0, a1, 7 3048# CHECK-INSTR: cv.insert.h a0, a1, 7 3049# CHECK-ENCODING: [0x7b,0xc5,0x35,0xba] 3050# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3051 3052cv.insert.h s0, s1, 63 3053# CHECK-INSTR: cv.insert.h s0, s1, 63 3054# CHECK-ENCODING: [0x7b,0xc4,0xf4,0xbb] 3055# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3056 3057//===----------------------------------------------------------------------===// 3058// cv.insert.b 3059//===----------------------------------------------------------------------===// 3060 3061cv.insert.b t0, t1, 0 3062# CHECK-INSTR: cv.insert.b t0, t1, 0 3063# CHECK-ENCODING: [0xfb,0x52,0x03,0xb8] 3064# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3065 3066cv.insert.b t3, t4, 32 3067# CHECK-INSTR: cv.insert.b t3, t4, 32 3068# CHECK-ENCODING: [0x7b,0xde,0x0e,0xb9] 3069# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3070 3071cv.insert.b a0, a1, 7 3072# CHECK-INSTR: cv.insert.b a0, a1, 7 3073# CHECK-ENCODING: [0x7b,0xd5,0x35,0xba] 3074# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3075 3076cv.insert.b s0, s1, 63 3077# CHECK-INSTR: cv.insert.b s0, s1, 63 3078# CHECK-ENCODING: [0x7b,0xd4,0xf4,0xbb] 3079# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3080 3081//===----------------------------------------------------------------------===// 3082// cv.shuffle.h 3083//===----------------------------------------------------------------------===// 3084 3085cv.shuffle.h t0, t1, t2 3086# CHECK-INSTR: cv.shuffle.h t0, t1, t2 3087# CHECK-ENCODING: [0xfb,0x02,0x73,0xc0] 3088# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3089 3090cv.shuffle.h t3, t4, t5 3091# CHECK-INSTR: cv.shuffle.h t3, t4, t5 3092# CHECK-ENCODING: [0x7b,0x8e,0xee,0xc1] 3093# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3094 3095cv.shuffle.h a0, a1, a2 3096# CHECK-INSTR: cv.shuffle.h a0, a1, a2 3097# CHECK-ENCODING: [0x7b,0x85,0xc5,0xc0] 3098# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3099 3100cv.shuffle.h s0, s1, s2 3101# CHECK-INSTR: cv.shuffle.h s0, s1, s2 3102# CHECK-ENCODING: [0x7b,0x84,0x24,0xc1] 3103# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3104 3105//===----------------------------------------------------------------------===// 3106// cv.shuffle.b 3107//===----------------------------------------------------------------------===// 3108 3109cv.shuffle.b t0, t1, t2 3110# CHECK-INSTR: cv.shuffle.b t0, t1, t2 3111# CHECK-ENCODING: [0xfb,0x12,0x73,0xc0] 3112# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3113 3114cv.shuffle.b t3, t4, t5 3115# CHECK-INSTR: cv.shuffle.b t3, t4, t5 3116# CHECK-ENCODING: [0x7b,0x9e,0xee,0xc1] 3117# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3118 3119cv.shuffle.b a0, a1, a2 3120# CHECK-INSTR: cv.shuffle.b a0, a1, a2 3121# CHECK-ENCODING: [0x7b,0x95,0xc5,0xc0] 3122# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3123 3124cv.shuffle.b s0, s1, s2 3125# CHECK-INSTR: cv.shuffle.b s0, s1, s2 3126# CHECK-ENCODING: [0x7b,0x94,0x24,0xc1] 3127# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3128 3129//===----------------------------------------------------------------------===// 3130// cv.shuffle.sci.h 3131//===----------------------------------------------------------------------===// 3132 3133cv.shuffle.sci.h t0, t1, 0 3134# CHECK-INSTR: cv.shuffle.sci.h t0, t1, 0 3135# CHECK-ENCODING: [0xfb,0x62,0x03,0xc0] 3136# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3137 3138cv.shuffle.sci.h t3, t4, 32 3139# CHECK-INSTR: cv.shuffle.sci.h t3, t4, 32 3140# CHECK-ENCODING: [0x7b,0xee,0x0e,0xc1] 3141# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3142 3143cv.shuffle.sci.h a0, a1, 7 3144# CHECK-INSTR: cv.shuffle.sci.h a0, a1, 7 3145# CHECK-ENCODING: [0x7b,0xe5,0x35,0xc2] 3146# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3147 3148cv.shuffle.sci.h s0, s1, 63 3149# CHECK-INSTR: cv.shuffle.sci.h s0, s1, 63 3150# CHECK-ENCODING: [0x7b,0xe4,0xf4,0xc3] 3151# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3152 3153//===----------------------------------------------------------------------===// 3154// cv.shuffleI0.sci.b 3155//===----------------------------------------------------------------------===// 3156 3157cv.shufflei0.sci.b t0, t1, 0 3158# CHECK-INSTR: cv.shufflei0.sci.b t0, t1, 0 3159# CHECK-ENCODING: [0xfb,0x72,0x03,0xc0] 3160# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3161 3162cv.shufflei0.sci.b t3, t4, 32 3163# CHECK-INSTR: cv.shufflei0.sci.b t3, t4, 32 3164# CHECK-ENCODING: [0x7b,0xfe,0x0e,0xc1] 3165# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3166 3167cv.shufflei0.sci.b a0, a1, 7 3168# CHECK-INSTR: cv.shufflei0.sci.b a0, a1, 7 3169# CHECK-ENCODING: [0x7b,0xf5,0x35,0xc2] 3170# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3171 3172cv.shufflei0.sci.b s0, s1, 63 3173# CHECK-INSTR: cv.shufflei0.sci.b s0, s1, 63 3174# CHECK-ENCODING: [0x7b,0xf4,0xf4,0xc3] 3175# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3176 3177//===----------------------------------------------------------------------===// 3178// cv.shuffleI1.sci.b 3179//===----------------------------------------------------------------------===// 3180 3181cv.shufflei1.sci.b t0, t1, 0 3182# CHECK-INSTR: cv.shufflei1.sci.b t0, t1, 0 3183# CHECK-ENCODING: [0xfb,0x72,0x03,0xc8] 3184# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3185 3186cv.shufflei1.sci.b t3, t4, 32 3187# CHECK-INSTR: cv.shufflei1.sci.b t3, t4, 32 3188# CHECK-ENCODING: [0x7b,0xfe,0x0e,0xc9] 3189# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3190 3191cv.shufflei1.sci.b a0, a1, 7 3192# CHECK-INSTR: cv.shufflei1.sci.b a0, a1, 7 3193# CHECK-ENCODING: [0x7b,0xf5,0x35,0xca] 3194# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3195 3196cv.shufflei1.sci.b s0, s1, 63 3197# CHECK-INSTR: cv.shufflei1.sci.b s0, s1, 63 3198# CHECK-ENCODING: [0x7b,0xf4,0xf4,0xcb] 3199# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3200 3201//===----------------------------------------------------------------------===// 3202// cv.shuffleI2.sci.b 3203//===----------------------------------------------------------------------===// 3204 3205cv.shufflei2.sci.b t0, t1, 0 3206# CHECK-INSTR: cv.shufflei2.sci.b t0, t1, 0 3207# CHECK-ENCODING: [0xfb,0x72,0x03,0xd0] 3208# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3209 3210cv.shufflei2.sci.b t3, t4, 32 3211# CHECK-INSTR: cv.shufflei2.sci.b t3, t4, 32 3212# CHECK-ENCODING: [0x7b,0xfe,0x0e,0xd1] 3213# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3214 3215cv.shufflei2.sci.b a0, a1, 7 3216# CHECK-INSTR: cv.shufflei2.sci.b a0, a1, 7 3217# CHECK-ENCODING: [0x7b,0xf5,0x35,0xd2] 3218# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3219 3220cv.shufflei2.sci.b s0, s1, 63 3221# CHECK-INSTR: cv.shufflei2.sci.b s0, s1, 63 3222# CHECK-ENCODING: [0x7b,0xf4,0xf4,0xd3] 3223# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3224 3225//===----------------------------------------------------------------------===// 3226// cv.shuffleI3.sci.b 3227//===----------------------------------------------------------------------===// 3228 3229cv.shufflei3.sci.b t0, t1, 0 3230# CHECK-INSTR: cv.shufflei3.sci.b t0, t1, 0 3231# CHECK-ENCODING: [0xfb,0x72,0x03,0xd8] 3232# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3233 3234cv.shufflei3.sci.b t3, t4, 32 3235# CHECK-INSTR: cv.shufflei3.sci.b t3, t4, 32 3236# CHECK-ENCODING: [0x7b,0xfe,0x0e,0xd9] 3237# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3238 3239cv.shufflei3.sci.b a0, a1, 7 3240# CHECK-INSTR: cv.shufflei3.sci.b a0, a1, 7 3241# CHECK-ENCODING: [0x7b,0xf5,0x35,0xda] 3242# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3243 3244cv.shufflei3.sci.b s0, s1, 63 3245# CHECK-INSTR: cv.shufflei3.sci.b s0, s1, 63 3246# CHECK-ENCODING: [0x7b,0xf4,0xf4,0xdb] 3247# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3248 3249//===----------------------------------------------------------------------===// 3250// cv.shuffle2.h 3251//===----------------------------------------------------------------------===// 3252 3253cv.shuffle2.h t0, t1, t2 3254# CHECK-INSTR: cv.shuffle2.h t0, t1, t2 3255# CHECK-ENCODING: [0xfb,0x02,0x73,0xe0] 3256# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3257 3258cv.shuffle2.h t3, t4, t5 3259# CHECK-INSTR: cv.shuffle2.h t3, t4, t5 3260# CHECK-ENCODING: [0x7b,0x8e,0xee,0xe1] 3261# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3262 3263cv.shuffle2.h a0, a1, a2 3264# CHECK-INSTR: cv.shuffle2.h a0, a1, a2 3265# CHECK-ENCODING: [0x7b,0x85,0xc5,0xe0] 3266# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3267 3268cv.shuffle2.h s0, s1, s2 3269# CHECK-INSTR: cv.shuffle2.h s0, s1, s2 3270# CHECK-ENCODING: [0x7b,0x84,0x24,0xe1] 3271# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3272 3273//===----------------------------------------------------------------------===// 3274// cv.shuffle2.b 3275//===----------------------------------------------------------------------===// 3276 3277cv.shuffle2.b t0, t1, t2 3278# CHECK-INSTR: cv.shuffle2.b t0, t1, t2 3279# CHECK-ENCODING: [0xfb,0x12,0x73,0xe0] 3280# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3281 3282cv.shuffle2.b t3, t4, t5 3283# CHECK-INSTR: cv.shuffle2.b t3, t4, t5 3284# CHECK-ENCODING: [0x7b,0x9e,0xee,0xe1] 3285# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3286 3287cv.shuffle2.b a0, a1, a2 3288# CHECK-INSTR: cv.shuffle2.b a0, a1, a2 3289# CHECK-ENCODING: [0x7b,0x95,0xc5,0xe0] 3290# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3291 3292cv.shuffle2.b s0, s1, s2 3293# CHECK-INSTR: cv.shuffle2.b s0, s1, s2 3294# CHECK-ENCODING: [0x7b,0x94,0x24,0xe1] 3295# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3296 3297//===----------------------------------------------------------------------===// 3298// cv.pack 3299//===----------------------------------------------------------------------===// 3300 3301cv.pack t0, t1, t2 3302# CHECK-INSTR: cv.pack t0, t1, t2 3303# CHECK-ENCODING: [0xfb,0x02,0x73,0xf0] 3304# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3305 3306cv.pack t3, t4, t5 3307# CHECK-INSTR: cv.pack t3, t4, t5 3308# CHECK-ENCODING: [0x7b,0x8e,0xee,0xf1] 3309# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3310 3311cv.pack a0, a1, a2 3312# CHECK-INSTR: cv.pack a0, a1, a2 3313# CHECK-ENCODING: [0x7b,0x85,0xc5,0xf0] 3314# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3315 3316cv.pack s0, s1, s2 3317# CHECK-INSTR: cv.pack s0, s1, s2 3318# CHECK-ENCODING: [0x7b,0x84,0x24,0xf1] 3319# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3320 3321//===----------------------------------------------------------------------===// 3322// cv.pack.h 3323//===----------------------------------------------------------------------===// 3324 3325cv.pack.h t0, t1, t2 3326# CHECK-INSTR: cv.pack.h t0, t1, t2 3327# CHECK-ENCODING: [0xfb,0x02,0x73,0xf2] 3328# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3329 3330cv.pack.h t3, t4, t5 3331# CHECK-INSTR: cv.pack.h t3, t4, t5 3332# CHECK-ENCODING: [0x7b,0x8e,0xee,0xf3] 3333# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3334 3335cv.pack.h a0, a1, a2 3336# CHECK-INSTR: cv.pack.h a0, a1, a2 3337# CHECK-ENCODING: [0x7b,0x85,0xc5,0xf2] 3338# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3339 3340cv.pack.h s0, s1, s2 3341# CHECK-INSTR: cv.pack.h s0, s1, s2 3342# CHECK-ENCODING: [0x7b,0x84,0x24,0xf3] 3343# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3344 3345//===----------------------------------------------------------------------===// 3346// cv.packhi.b 3347//===----------------------------------------------------------------------===// 3348 3349cv.packhi.b t0, t1, t2 3350# CHECK-INSTR: cv.packhi.b t0, t1, t2 3351# CHECK-ENCODING: [0xfb,0x12,0x73,0xfa] 3352# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3353 3354cv.packhi.b t3, t4, t5 3355# CHECK-INSTR: cv.packhi.b t3, t4, t5 3356# CHECK-ENCODING: [0x7b,0x9e,0xee,0xfb] 3357# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3358 3359cv.packhi.b a0, a1, a2 3360# CHECK-INSTR: cv.packhi.b a0, a1, a2 3361# CHECK-ENCODING: [0x7b,0x95,0xc5,0xfa] 3362# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3363 3364cv.packhi.b s0, s1, s2 3365# CHECK-INSTR: cv.packhi.b s0, s1, s2 3366# CHECK-ENCODING: [0x7b,0x94,0x24,0xfb] 3367# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3368 3369//===----------------------------------------------------------------------===// 3370// cv.packlo.b 3371//===----------------------------------------------------------------------===// 3372 3373cv.packlo.b t0, t1, t2 3374# CHECK-INSTR: cv.packlo.b t0, t1, t2 3375# CHECK-ENCODING: [0xfb,0x12,0x73,0xf8] 3376# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3377 3378cv.packlo.b t3, t4, t5 3379# CHECK-INSTR: cv.packlo.b t3, t4, t5 3380# CHECK-ENCODING: [0x7b,0x9e,0xee,0xf9] 3381# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3382 3383cv.packlo.b a0, a1, a2 3384# CHECK-INSTR: cv.packlo.b a0, a1, a2 3385# CHECK-ENCODING: [0x7b,0x95,0xc5,0xf8] 3386# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3387 3388cv.packlo.b s0, s1, s2 3389# CHECK-INSTR: cv.packlo.b s0, s1, s2 3390# CHECK-ENCODING: [0x7b,0x94,0x24,0xf9] 3391# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3392 3393//===----------------------------------------------------------------------===// 3394// cv.cmpeq.h 3395//===----------------------------------------------------------------------===// 3396 3397cv.cmpeq.h t0, t1, t2 3398# CHECK-INSTR: cv.cmpeq.h t0, t1, t2 3399# CHECK-ENCODING: [0xfb,0x02,0x73,0x04] 3400# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3401 3402cv.cmpeq.h t3, t4, t5 3403# CHECK-INSTR: cv.cmpeq.h t3, t4, t5 3404# CHECK-ENCODING: [0x7b,0x8e,0xee,0x05] 3405# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3406 3407cv.cmpeq.h a0, a1, a2 3408# CHECK-INSTR: cv.cmpeq.h a0, a1, a2 3409# CHECK-ENCODING: [0x7b,0x85,0xc5,0x04] 3410# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3411 3412cv.cmpeq.h s0, s1, s2 3413# CHECK-INSTR: cv.cmpeq.h s0, s1, s2 3414# CHECK-ENCODING: [0x7b,0x84,0x24,0x05] 3415# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3416 3417//===----------------------------------------------------------------------===// 3418// cv.cmpeq.b 3419//===----------------------------------------------------------------------===// 3420 3421cv.cmpeq.b t0, t1, t2 3422# CHECK-INSTR: cv.cmpeq.b t0, t1, t2 3423# CHECK-ENCODING: [0xfb,0x12,0x73,0x04] 3424# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3425 3426cv.cmpeq.b t3, t4, t5 3427# CHECK-INSTR: cv.cmpeq.b t3, t4, t5 3428# CHECK-ENCODING: [0x7b,0x9e,0xee,0x05] 3429# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3430 3431cv.cmpeq.b a0, a1, a2 3432# CHECK-INSTR: cv.cmpeq.b a0, a1, a2 3433# CHECK-ENCODING: [0x7b,0x95,0xc5,0x04] 3434# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3435 3436cv.cmpeq.b s0, s1, s2 3437# CHECK-INSTR: cv.cmpeq.b s0, s1, s2 3438# CHECK-ENCODING: [0x7b,0x94,0x24,0x05] 3439# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3440 3441//===----------------------------------------------------------------------===// 3442// cv.cmpeq.sc.h 3443//===----------------------------------------------------------------------===// 3444 3445cv.cmpeq.sc.h t0, t1, t2 3446# CHECK-INSTR: cv.cmpeq.sc.h t0, t1, t2 3447# CHECK-ENCODING: [0xfb,0x42,0x73,0x04] 3448# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3449 3450cv.cmpeq.sc.h t3, t4, t5 3451# CHECK-INSTR: cv.cmpeq.sc.h t3, t4, t5 3452# CHECK-ENCODING: [0x7b,0xce,0xee,0x05] 3453# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3454 3455cv.cmpeq.sc.h a0, a1, a2 3456# CHECK-INSTR: cv.cmpeq.sc.h a0, a1, a2 3457# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x04] 3458# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3459 3460cv.cmpeq.sc.h s0, s1, s2 3461# CHECK-INSTR: cv.cmpeq.sc.h s0, s1, s2 3462# CHECK-ENCODING: [0x7b,0xc4,0x24,0x05] 3463# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3464 3465//===----------------------------------------------------------------------===// 3466// cv.cmpeq.sc.b 3467//===----------------------------------------------------------------------===// 3468 3469cv.cmpeq.sc.b t0, t1, t2 3470# CHECK-INSTR: cv.cmpeq.sc.b t0, t1, t2 3471# CHECK-ENCODING: [0xfb,0x52,0x73,0x04] 3472# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3473 3474cv.cmpeq.sc.b t3, t4, t5 3475# CHECK-INSTR: cv.cmpeq.sc.b t3, t4, t5 3476# CHECK-ENCODING: [0x7b,0xde,0xee,0x05] 3477# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3478 3479cv.cmpeq.sc.b a0, a1, a2 3480# CHECK-INSTR: cv.cmpeq.sc.b a0, a1, a2 3481# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x04] 3482# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3483 3484cv.cmpeq.sc.b s0, s1, s2 3485# CHECK-INSTR: cv.cmpeq.sc.b s0, s1, s2 3486# CHECK-ENCODING: [0x7b,0xd4,0x24,0x05] 3487# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3488 3489//===----------------------------------------------------------------------===// 3490// cv.cmpeq.sci.h 3491//===----------------------------------------------------------------------===// 3492 3493cv.cmpeq.sci.h t0, t1, 0 3494# CHECK-INSTR: cv.cmpeq.sci.h t0, t1, 0 3495# CHECK-ENCODING: [0xfb,0x62,0x03,0x04] 3496# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3497 3498cv.cmpeq.sci.h t3, t4, -32 3499# CHECK-INSTR: cv.cmpeq.sci.h t3, t4, -32 3500# CHECK-ENCODING: [0x7b,0xee,0x0e,0x05] 3501# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3502 3503cv.cmpeq.sci.h a0, a1, 7 3504# CHECK-INSTR: cv.cmpeq.sci.h a0, a1, 7 3505# CHECK-ENCODING: [0x7b,0xe5,0x35,0x06] 3506# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3507 3508cv.cmpeq.sci.h s0, s1, -1 3509# CHECK-INSTR: cv.cmpeq.sci.h s0, s1, -1 3510# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x07] 3511# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3512 3513//===----------------------------------------------------------------------===// 3514// cv.cmpeq.sci.b 3515//===----------------------------------------------------------------------===// 3516 3517cv.cmpeq.sci.b t0, t1, 0 3518# CHECK-INSTR: cv.cmpeq.sci.b t0, t1, 0 3519# CHECK-ENCODING: [0xfb,0x72,0x03,0x04] 3520# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3521 3522cv.cmpeq.sci.b t3, t4, -32 3523# CHECK-INSTR: cv.cmpeq.sci.b t3, t4, -32 3524# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x05] 3525# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3526 3527cv.cmpeq.sci.b a0, a1, 7 3528# CHECK-INSTR: cv.cmpeq.sci.b a0, a1, 7 3529# CHECK-ENCODING: [0x7b,0xf5,0x35,0x06] 3530# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3531 3532cv.cmpeq.sci.b s0, s1, -1 3533# CHECK-INSTR: cv.cmpeq.sci.b s0, s1, -1 3534# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x07] 3535# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3536 3537//===----------------------------------------------------------------------===// 3538// cv.cmpne.h 3539//===----------------------------------------------------------------------===// 3540 3541cv.cmpne.h t0, t1, t2 3542# CHECK-INSTR: cv.cmpne.h t0, t1, t2 3543# CHECK-ENCODING: [0xfb,0x02,0x73,0x0c] 3544# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3545 3546cv.cmpne.h t3, t4, t5 3547# CHECK-INSTR: cv.cmpne.h t3, t4, t5 3548# CHECK-ENCODING: [0x7b,0x8e,0xee,0x0d] 3549# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3550 3551cv.cmpne.h a0, a1, a2 3552# CHECK-INSTR: cv.cmpne.h a0, a1, a2 3553# CHECK-ENCODING: [0x7b,0x85,0xc5,0x0c] 3554# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3555 3556cv.cmpne.h s0, s1, s2 3557# CHECK-INSTR: cv.cmpne.h s0, s1, s2 3558# CHECK-ENCODING: [0x7b,0x84,0x24,0x0d] 3559# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3560 3561//===----------------------------------------------------------------------===// 3562// cv.cmpne.b 3563//===----------------------------------------------------------------------===// 3564 3565cv.cmpne.b t0, t1, t2 3566# CHECK-INSTR: cv.cmpne.b t0, t1, t2 3567# CHECK-ENCODING: [0xfb,0x12,0x73,0x0c] 3568# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3569 3570cv.cmpne.b t3, t4, t5 3571# CHECK-INSTR: cv.cmpne.b t3, t4, t5 3572# CHECK-ENCODING: [0x7b,0x9e,0xee,0x0d] 3573# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3574 3575cv.cmpne.b a0, a1, a2 3576# CHECK-INSTR: cv.cmpne.b a0, a1, a2 3577# CHECK-ENCODING: [0x7b,0x95,0xc5,0x0c] 3578# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3579 3580cv.cmpne.b s0, s1, s2 3581# CHECK-INSTR: cv.cmpne.b s0, s1, s2 3582# CHECK-ENCODING: [0x7b,0x94,0x24,0x0d] 3583# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3584 3585//===----------------------------------------------------------------------===// 3586// cv.cmpne.sc.h 3587//===----------------------------------------------------------------------===// 3588 3589cv.cmpne.sc.h t0, t1, t2 3590# CHECK-INSTR: cv.cmpne.sc.h t0, t1, t2 3591# CHECK-ENCODING: [0xfb,0x42,0x73,0x0c] 3592# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3593 3594cv.cmpne.sc.h t3, t4, t5 3595# CHECK-INSTR: cv.cmpne.sc.h t3, t4, t5 3596# CHECK-ENCODING: [0x7b,0xce,0xee,0x0d] 3597# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3598 3599cv.cmpne.sc.h a0, a1, a2 3600# CHECK-INSTR: cv.cmpne.sc.h a0, a1, a2 3601# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x0c] 3602# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3603 3604cv.cmpne.sc.h s0, s1, s2 3605# CHECK-INSTR: cv.cmpne.sc.h s0, s1, s2 3606# CHECK-ENCODING: [0x7b,0xc4,0x24,0x0d] 3607# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3608 3609//===----------------------------------------------------------------------===// 3610// cv.cmpne.sc.b 3611//===----------------------------------------------------------------------===// 3612 3613cv.cmpne.sc.b t0, t1, t2 3614# CHECK-INSTR: cv.cmpne.sc.b t0, t1, t2 3615# CHECK-ENCODING: [0xfb,0x52,0x73,0x0c] 3616# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3617 3618cv.cmpne.sc.b t3, t4, t5 3619# CHECK-INSTR: cv.cmpne.sc.b t3, t4, t5 3620# CHECK-ENCODING: [0x7b,0xde,0xee,0x0d] 3621# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3622 3623cv.cmpne.sc.b a0, a1, a2 3624# CHECK-INSTR: cv.cmpne.sc.b a0, a1, a2 3625# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x0c] 3626# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3627 3628cv.cmpne.sc.b s0, s1, s2 3629# CHECK-INSTR: cv.cmpne.sc.b s0, s1, s2 3630# CHECK-ENCODING: [0x7b,0xd4,0x24,0x0d] 3631# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3632 3633//===----------------------------------------------------------------------===// 3634// cv.cmpne.sci.h 3635//===----------------------------------------------------------------------===// 3636 3637cv.cmpne.sci.h t0, t1, 0 3638# CHECK-INSTR: cv.cmpne.sci.h t0, t1, 0 3639# CHECK-ENCODING: [0xfb,0x62,0x03,0x0c] 3640# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3641 3642cv.cmpne.sci.h t3, t4, -32 3643# CHECK-INSTR: cv.cmpne.sci.h t3, t4, -32 3644# CHECK-ENCODING: [0x7b,0xee,0x0e,0x0d] 3645# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3646 3647cv.cmpne.sci.h a0, a1, 7 3648# CHECK-INSTR: cv.cmpne.sci.h a0, a1, 7 3649# CHECK-ENCODING: [0x7b,0xe5,0x35,0x0e] 3650# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3651 3652cv.cmpne.sci.h s0, s1, -1 3653# CHECK-INSTR: cv.cmpne.sci.h s0, s1, -1 3654# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x0f] 3655# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3656 3657//===----------------------------------------------------------------------===// 3658// cv.cmpne.sci.b 3659//===----------------------------------------------------------------------===// 3660 3661cv.cmpne.sci.b t0, t1, 0 3662# CHECK-INSTR: cv.cmpne.sci.b t0, t1, 0 3663# CHECK-ENCODING: [0xfb,0x72,0x03,0x0c] 3664# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3665 3666cv.cmpne.sci.b t3, t4, -32 3667# CHECK-INSTR: cv.cmpne.sci.b t3, t4, -32 3668# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x0d] 3669# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3670 3671cv.cmpne.sci.b a0, a1, 7 3672# CHECK-INSTR: cv.cmpne.sci.b a0, a1, 7 3673# CHECK-ENCODING: [0x7b,0xf5,0x35,0x0e] 3674# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3675 3676cv.cmpne.sci.b s0, s1, -1 3677# CHECK-INSTR: cv.cmpne.sci.b s0, s1, -1 3678# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x0f] 3679# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3680 3681//===----------------------------------------------------------------------===// 3682// cv.cmpgt.h 3683//===----------------------------------------------------------------------===// 3684 3685cv.cmpgt.h t0, t1, t2 3686# CHECK-INSTR: cv.cmpgt.h t0, t1, t2 3687# CHECK-ENCODING: [0xfb,0x02,0x73,0x14] 3688# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3689 3690cv.cmpgt.h t3, t4, t5 3691# CHECK-INSTR: cv.cmpgt.h t3, t4, t5 3692# CHECK-ENCODING: [0x7b,0x8e,0xee,0x15] 3693# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3694 3695cv.cmpgt.h a0, a1, a2 3696# CHECK-INSTR: cv.cmpgt.h a0, a1, a2 3697# CHECK-ENCODING: [0x7b,0x85,0xc5,0x14] 3698# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3699 3700cv.cmpgt.h s0, s1, s2 3701# CHECK-INSTR: cv.cmpgt.h s0, s1, s2 3702# CHECK-ENCODING: [0x7b,0x84,0x24,0x15] 3703# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3704 3705//===----------------------------------------------------------------------===// 3706// cv.cmpgt.b 3707//===----------------------------------------------------------------------===// 3708 3709cv.cmpgt.b t0, t1, t2 3710# CHECK-INSTR: cv.cmpgt.b t0, t1, t2 3711# CHECK-ENCODING: [0xfb,0x12,0x73,0x14] 3712# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3713 3714cv.cmpgt.b t3, t4, t5 3715# CHECK-INSTR: cv.cmpgt.b t3, t4, t5 3716# CHECK-ENCODING: [0x7b,0x9e,0xee,0x15] 3717# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3718 3719cv.cmpgt.b a0, a1, a2 3720# CHECK-INSTR: cv.cmpgt.b a0, a1, a2 3721# CHECK-ENCODING: [0x7b,0x95,0xc5,0x14] 3722# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3723 3724cv.cmpgt.b s0, s1, s2 3725# CHECK-INSTR: cv.cmpgt.b s0, s1, s2 3726# CHECK-ENCODING: [0x7b,0x94,0x24,0x15] 3727# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3728 3729//===----------------------------------------------------------------------===// 3730// cv.cmpgt.sc.h 3731//===----------------------------------------------------------------------===// 3732 3733cv.cmpgt.sc.h t0, t1, t2 3734# CHECK-INSTR: cv.cmpgt.sc.h t0, t1, t2 3735# CHECK-ENCODING: [0xfb,0x42,0x73,0x14] 3736# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3737 3738cv.cmpgt.sc.h t3, t4, t5 3739# CHECK-INSTR: cv.cmpgt.sc.h t3, t4, t5 3740# CHECK-ENCODING: [0x7b,0xce,0xee,0x15] 3741# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3742 3743cv.cmpgt.sc.h a0, a1, a2 3744# CHECK-INSTR: cv.cmpgt.sc.h a0, a1, a2 3745# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x14] 3746# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3747 3748cv.cmpgt.sc.h s0, s1, s2 3749# CHECK-INSTR: cv.cmpgt.sc.h s0, s1, s2 3750# CHECK-ENCODING: [0x7b,0xc4,0x24,0x15] 3751# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3752 3753//===----------------------------------------------------------------------===// 3754// cv.cmpgt.sc.b 3755//===----------------------------------------------------------------------===// 3756 3757cv.cmpgt.sc.b t0, t1, t2 3758# CHECK-INSTR: cv.cmpgt.sc.b t0, t1, t2 3759# CHECK-ENCODING: [0xfb,0x52,0x73,0x14] 3760# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3761 3762cv.cmpgt.sc.b t3, t4, t5 3763# CHECK-INSTR: cv.cmpgt.sc.b t3, t4, t5 3764# CHECK-ENCODING: [0x7b,0xde,0xee,0x15] 3765# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3766 3767cv.cmpgt.sc.b a0, a1, a2 3768# CHECK-INSTR: cv.cmpgt.sc.b a0, a1, a2 3769# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x14] 3770# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3771 3772cv.cmpgt.sc.b s0, s1, s2 3773# CHECK-INSTR: cv.cmpgt.sc.b s0, s1, s2 3774# CHECK-ENCODING: [0x7b,0xd4,0x24,0x15] 3775# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3776 3777//===----------------------------------------------------------------------===// 3778// cv.cmpgt.sci.h 3779//===----------------------------------------------------------------------===// 3780 3781cv.cmpgt.sci.h t0, t1, 0 3782# CHECK-INSTR: cv.cmpgt.sci.h t0, t1, 0 3783# CHECK-ENCODING: [0xfb,0x62,0x03,0x14] 3784# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3785 3786cv.cmpgt.sci.h t3, t4, -32 3787# CHECK-INSTR: cv.cmpgt.sci.h t3, t4, -32 3788# CHECK-ENCODING: [0x7b,0xee,0x0e,0x15] 3789# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3790 3791cv.cmpgt.sci.h a0, a1, 7 3792# CHECK-INSTR: cv.cmpgt.sci.h a0, a1, 7 3793# CHECK-ENCODING: [0x7b,0xe5,0x35,0x16] 3794# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3795 3796cv.cmpgt.sci.h s0, s1, -1 3797# CHECK-INSTR: cv.cmpgt.sci.h s0, s1, -1 3798# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x17] 3799# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3800 3801//===----------------------------------------------------------------------===// 3802// cv.cmpgt.sci.b 3803//===----------------------------------------------------------------------===// 3804 3805cv.cmpgt.sci.b t0, t1, 0 3806# CHECK-INSTR: cv.cmpgt.sci.b t0, t1, 0 3807# CHECK-ENCODING: [0xfb,0x72,0x03,0x14] 3808# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3809 3810cv.cmpgt.sci.b t3, t4, -32 3811# CHECK-INSTR: cv.cmpgt.sci.b t3, t4, -32 3812# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x15] 3813# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3814 3815cv.cmpgt.sci.b a0, a1, 7 3816# CHECK-INSTR: cv.cmpgt.sci.b a0, a1, 7 3817# CHECK-ENCODING: [0x7b,0xf5,0x35,0x16] 3818# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3819 3820cv.cmpgt.sci.b s0, s1, -1 3821# CHECK-INSTR: cv.cmpgt.sci.b s0, s1, -1 3822# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x17] 3823# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3824 3825//===----------------------------------------------------------------------===// 3826// cv.cmpge.h 3827//===----------------------------------------------------------------------===// 3828 3829cv.cmpge.h t0, t1, t2 3830# CHECK-INSTR: cv.cmpge.h t0, t1, t2 3831# CHECK-ENCODING: [0xfb,0x02,0x73,0x1c] 3832# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3833 3834cv.cmpge.h t3, t4, t5 3835# CHECK-INSTR: cv.cmpge.h t3, t4, t5 3836# CHECK-ENCODING: [0x7b,0x8e,0xee,0x1d] 3837# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3838 3839cv.cmpge.h a0, a1, a2 3840# CHECK-INSTR: cv.cmpge.h a0, a1, a2 3841# CHECK-ENCODING: [0x7b,0x85,0xc5,0x1c] 3842# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3843 3844cv.cmpge.h s0, s1, s2 3845# CHECK-INSTR: cv.cmpge.h s0, s1, s2 3846# CHECK-ENCODING: [0x7b,0x84,0x24,0x1d] 3847# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3848 3849//===----------------------------------------------------------------------===// 3850// cv.cmpge.b 3851//===----------------------------------------------------------------------===// 3852 3853cv.cmpge.b t0, t1, t2 3854# CHECK-INSTR: cv.cmpge.b t0, t1, t2 3855# CHECK-ENCODING: [0xfb,0x12,0x73,0x1c] 3856# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3857 3858cv.cmpge.b t3, t4, t5 3859# CHECK-INSTR: cv.cmpge.b t3, t4, t5 3860# CHECK-ENCODING: [0x7b,0x9e,0xee,0x1d] 3861# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3862 3863cv.cmpge.b a0, a1, a2 3864# CHECK-INSTR: cv.cmpge.b a0, a1, a2 3865# CHECK-ENCODING: [0x7b,0x95,0xc5,0x1c] 3866# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3867 3868cv.cmpge.b s0, s1, s2 3869# CHECK-INSTR: cv.cmpge.b s0, s1, s2 3870# CHECK-ENCODING: [0x7b,0x94,0x24,0x1d] 3871# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3872 3873//===----------------------------------------------------------------------===// 3874// cv.cmpge.sc.h 3875//===----------------------------------------------------------------------===// 3876 3877cv.cmpge.sc.h t0, t1, t2 3878# CHECK-INSTR: cv.cmpge.sc.h t0, t1, t2 3879# CHECK-ENCODING: [0xfb,0x42,0x73,0x1c] 3880# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3881 3882cv.cmpge.sc.h t3, t4, t5 3883# CHECK-INSTR: cv.cmpge.sc.h t3, t4, t5 3884# CHECK-ENCODING: [0x7b,0xce,0xee,0x1d] 3885# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3886 3887cv.cmpge.sc.h a0, a1, a2 3888# CHECK-INSTR: cv.cmpge.sc.h a0, a1, a2 3889# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x1c] 3890# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3891 3892cv.cmpge.sc.h s0, s1, s2 3893# CHECK-INSTR: cv.cmpge.sc.h s0, s1, s2 3894# CHECK-ENCODING: [0x7b,0xc4,0x24,0x1d] 3895# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3896 3897//===----------------------------------------------------------------------===// 3898// cv.cmpge.sc.b 3899//===----------------------------------------------------------------------===// 3900 3901cv.cmpge.sc.b t0, t1, t2 3902# CHECK-INSTR: cv.cmpge.sc.b t0, t1, t2 3903# CHECK-ENCODING: [0xfb,0x52,0x73,0x1c] 3904# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3905 3906cv.cmpge.sc.b t3, t4, t5 3907# CHECK-INSTR: cv.cmpge.sc.b t3, t4, t5 3908# CHECK-ENCODING: [0x7b,0xde,0xee,0x1d] 3909# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3910 3911cv.cmpge.sc.b a0, a1, a2 3912# CHECK-INSTR: cv.cmpge.sc.b a0, a1, a2 3913# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x1c] 3914# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3915 3916cv.cmpge.sc.b s0, s1, s2 3917# CHECK-INSTR: cv.cmpge.sc.b s0, s1, s2 3918# CHECK-ENCODING: [0x7b,0xd4,0x24,0x1d] 3919# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3920 3921//===----------------------------------------------------------------------===// 3922// cv.cmpge.sci.h 3923//===----------------------------------------------------------------------===// 3924 3925cv.cmpge.sci.h t0, t1, 0 3926# CHECK-INSTR: cv.cmpge.sci.h t0, t1, 0 3927# CHECK-ENCODING: [0xfb,0x62,0x03,0x1c] 3928# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3929 3930cv.cmpge.sci.h t3, t4, -32 3931# CHECK-INSTR: cv.cmpge.sci.h t3, t4, -32 3932# CHECK-ENCODING: [0x7b,0xee,0x0e,0x1d] 3933# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3934 3935cv.cmpge.sci.h a0, a1, 7 3936# CHECK-INSTR: cv.cmpge.sci.h a0, a1, 7 3937# CHECK-ENCODING: [0x7b,0xe5,0x35,0x1e] 3938# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3939 3940cv.cmpge.sci.h s0, s1, -1 3941# CHECK-INSTR: cv.cmpge.sci.h s0, s1, -1 3942# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x1f] 3943# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3944 3945//===----------------------------------------------------------------------===// 3946// cv.cmpge.sci.b 3947//===----------------------------------------------------------------------===// 3948 3949cv.cmpge.sci.b t0, t1, 0 3950# CHECK-INSTR: cv.cmpge.sci.b t0, t1, 0 3951# CHECK-ENCODING: [0xfb,0x72,0x03,0x1c] 3952# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3953 3954cv.cmpge.sci.b t3, t4, -32 3955# CHECK-INSTR: cv.cmpge.sci.b t3, t4, -32 3956# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x1d] 3957# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3958 3959cv.cmpge.sci.b a0, a1, 7 3960# CHECK-INSTR: cv.cmpge.sci.b a0, a1, 7 3961# CHECK-ENCODING: [0x7b,0xf5,0x35,0x1e] 3962# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3963 3964cv.cmpge.sci.b s0, s1, -1 3965# CHECK-INSTR: cv.cmpge.sci.b s0, s1, -1 3966# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x1f] 3967# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3968 3969//===----------------------------------------------------------------------===// 3970// cv.cmplt.h 3971//===----------------------------------------------------------------------===// 3972 3973cv.cmplt.h t0, t1, t2 3974# CHECK-INSTR: cv.cmplt.h t0, t1, t2 3975# CHECK-ENCODING: [0xfb,0x02,0x73,0x24] 3976# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3977 3978cv.cmplt.h t3, t4, t5 3979# CHECK-INSTR: cv.cmplt.h t3, t4, t5 3980# CHECK-ENCODING: [0x7b,0x8e,0xee,0x25] 3981# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3982 3983cv.cmplt.h a0, a1, a2 3984# CHECK-INSTR: cv.cmplt.h a0, a1, a2 3985# CHECK-ENCODING: [0x7b,0x85,0xc5,0x24] 3986# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3987 3988cv.cmplt.h s0, s1, s2 3989# CHECK-INSTR: cv.cmplt.h s0, s1, s2 3990# CHECK-ENCODING: [0x7b,0x84,0x24,0x25] 3991# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 3992 3993//===----------------------------------------------------------------------===// 3994// cv.cmplt.b 3995//===----------------------------------------------------------------------===// 3996 3997cv.cmplt.b t0, t1, t2 3998# CHECK-INSTR: cv.cmplt.b t0, t1, t2 3999# CHECK-ENCODING: [0xfb,0x12,0x73,0x24] 4000# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4001 4002cv.cmplt.b t3, t4, t5 4003# CHECK-INSTR: cv.cmplt.b t3, t4, t5 4004# CHECK-ENCODING: [0x7b,0x9e,0xee,0x25] 4005# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4006 4007cv.cmplt.b a0, a1, a2 4008# CHECK-INSTR: cv.cmplt.b a0, a1, a2 4009# CHECK-ENCODING: [0x7b,0x95,0xc5,0x24] 4010# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4011 4012cv.cmplt.b s0, s1, s2 4013# CHECK-INSTR: cv.cmplt.b s0, s1, s2 4014# CHECK-ENCODING: [0x7b,0x94,0x24,0x25] 4015# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4016 4017//===----------------------------------------------------------------------===// 4018// cv.cmplt.sc.h 4019//===----------------------------------------------------------------------===// 4020 4021cv.cmplt.sc.h t0, t1, t2 4022# CHECK-INSTR: cv.cmplt.sc.h t0, t1, t2 4023# CHECK-ENCODING: [0xfb,0x42,0x73,0x24] 4024# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4025 4026cv.cmplt.sc.h t3, t4, t5 4027# CHECK-INSTR: cv.cmplt.sc.h t3, t4, t5 4028# CHECK-ENCODING: [0x7b,0xce,0xee,0x25] 4029# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4030 4031cv.cmplt.sc.h a0, a1, a2 4032# CHECK-INSTR: cv.cmplt.sc.h a0, a1, a2 4033# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x24] 4034# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4035 4036cv.cmplt.sc.h s0, s1, s2 4037# CHECK-INSTR: cv.cmplt.sc.h s0, s1, s2 4038# CHECK-ENCODING: [0x7b,0xc4,0x24,0x25] 4039# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4040 4041//===----------------------------------------------------------------------===// 4042// cv.cmplt.sc.b 4043//===----------------------------------------------------------------------===// 4044 4045cv.cmplt.sc.b t0, t1, t2 4046# CHECK-INSTR: cv.cmplt.sc.b t0, t1, t2 4047# CHECK-ENCODING: [0xfb,0x52,0x73,0x24] 4048# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4049 4050cv.cmplt.sc.b t3, t4, t5 4051# CHECK-INSTR: cv.cmplt.sc.b t3, t4, t5 4052# CHECK-ENCODING: [0x7b,0xde,0xee,0x25] 4053# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4054 4055cv.cmplt.sc.b a0, a1, a2 4056# CHECK-INSTR: cv.cmplt.sc.b a0, a1, a2 4057# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x24] 4058# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4059 4060cv.cmplt.sc.b s0, s1, s2 4061# CHECK-INSTR: cv.cmplt.sc.b s0, s1, s2 4062# CHECK-ENCODING: [0x7b,0xd4,0x24,0x25] 4063# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4064 4065//===----------------------------------------------------------------------===// 4066// cv.cmplt.sci.h 4067//===----------------------------------------------------------------------===// 4068 4069cv.cmplt.sci.h t0, t1, 0 4070# CHECK-INSTR: cv.cmplt.sci.h t0, t1, 0 4071# CHECK-ENCODING: [0xfb,0x62,0x03,0x24] 4072# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4073 4074cv.cmplt.sci.h t3, t4, -32 4075# CHECK-INSTR: cv.cmplt.sci.h t3, t4, -32 4076# CHECK-ENCODING: [0x7b,0xee,0x0e,0x25] 4077# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4078 4079cv.cmplt.sci.h a0, a1, 7 4080# CHECK-INSTR: cv.cmplt.sci.h a0, a1, 7 4081# CHECK-ENCODING: [0x7b,0xe5,0x35,0x26] 4082# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4083 4084cv.cmplt.sci.h s0, s1, -1 4085# CHECK-INSTR: cv.cmplt.sci.h s0, s1, -1 4086# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x27] 4087# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4088 4089//===----------------------------------------------------------------------===// 4090// cv.cmplt.sci.b 4091//===----------------------------------------------------------------------===// 4092 4093cv.cmplt.sci.b t0, t1, 0 4094# CHECK-INSTR: cv.cmplt.sci.b t0, t1, 0 4095# CHECK-ENCODING: [0xfb,0x72,0x03,0x24] 4096# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4097 4098cv.cmplt.sci.b t3, t4, -32 4099# CHECK-INSTR: cv.cmplt.sci.b t3, t4, -32 4100# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x25] 4101# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4102 4103cv.cmplt.sci.b a0, a1, 7 4104# CHECK-INSTR: cv.cmplt.sci.b a0, a1, 7 4105# CHECK-ENCODING: [0x7b,0xf5,0x35,0x26] 4106# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4107 4108cv.cmplt.sci.b s0, s1, -1 4109# CHECK-INSTR: cv.cmplt.sci.b s0, s1, -1 4110# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x27] 4111# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4112 4113//===----------------------------------------------------------------------===// 4114// cv.cmple.h 4115//===----------------------------------------------------------------------===// 4116 4117cv.cmple.h t0, t1, t2 4118# CHECK-INSTR: cv.cmple.h t0, t1, t2 4119# CHECK-ENCODING: [0xfb,0x02,0x73,0x2c] 4120# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4121 4122cv.cmple.h t3, t4, t5 4123# CHECK-INSTR: cv.cmple.h t3, t4, t5 4124# CHECK-ENCODING: [0x7b,0x8e,0xee,0x2d] 4125# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4126 4127cv.cmple.h a0, a1, a2 4128# CHECK-INSTR: cv.cmple.h a0, a1, a2 4129# CHECK-ENCODING: [0x7b,0x85,0xc5,0x2c] 4130# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4131 4132cv.cmple.h s0, s1, s2 4133# CHECK-INSTR: cv.cmple.h s0, s1, s2 4134# CHECK-ENCODING: [0x7b,0x84,0x24,0x2d] 4135# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4136 4137//===----------------------------------------------------------------------===// 4138// cv.cmple.b 4139//===----------------------------------------------------------------------===// 4140 4141cv.cmple.b t0, t1, t2 4142# CHECK-INSTR: cv.cmple.b t0, t1, t2 4143# CHECK-ENCODING: [0xfb,0x12,0x73,0x2c] 4144# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4145 4146cv.cmple.b t3, t4, t5 4147# CHECK-INSTR: cv.cmple.b t3, t4, t5 4148# CHECK-ENCODING: [0x7b,0x9e,0xee,0x2d] 4149# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4150 4151cv.cmple.b a0, a1, a2 4152# CHECK-INSTR: cv.cmple.b a0, a1, a2 4153# CHECK-ENCODING: [0x7b,0x95,0xc5,0x2c] 4154# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4155 4156cv.cmple.b s0, s1, s2 4157# CHECK-INSTR: cv.cmple.b s0, s1, s2 4158# CHECK-ENCODING: [0x7b,0x94,0x24,0x2d] 4159# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4160 4161//===----------------------------------------------------------------------===// 4162// cv.cmple.sc.h 4163//===----------------------------------------------------------------------===// 4164 4165cv.cmple.sc.h t0, t1, t2 4166# CHECK-INSTR: cv.cmple.sc.h t0, t1, t2 4167# CHECK-ENCODING: [0xfb,0x42,0x73,0x2c] 4168# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4169 4170cv.cmple.sc.h t3, t4, t5 4171# CHECK-INSTR: cv.cmple.sc.h t3, t4, t5 4172# CHECK-ENCODING: [0x7b,0xce,0xee,0x2d] 4173# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4174 4175cv.cmple.sc.h a0, a1, a2 4176# CHECK-INSTR: cv.cmple.sc.h a0, a1, a2 4177# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x2c] 4178# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4179 4180cv.cmple.sc.h s0, s1, s2 4181# CHECK-INSTR: cv.cmple.sc.h s0, s1, s2 4182# CHECK-ENCODING: [0x7b,0xc4,0x24,0x2d] 4183# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4184 4185//===----------------------------------------------------------------------===// 4186// cv.cmple.sc.b 4187//===----------------------------------------------------------------------===// 4188 4189cv.cmple.sc.b t0, t1, t2 4190# CHECK-INSTR: cv.cmple.sc.b t0, t1, t2 4191# CHECK-ENCODING: [0xfb,0x52,0x73,0x2c] 4192# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4193 4194cv.cmple.sc.b t3, t4, t5 4195# CHECK-INSTR: cv.cmple.sc.b t3, t4, t5 4196# CHECK-ENCODING: [0x7b,0xde,0xee,0x2d] 4197# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4198 4199cv.cmple.sc.b a0, a1, a2 4200# CHECK-INSTR: cv.cmple.sc.b a0, a1, a2 4201# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x2c] 4202# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4203 4204cv.cmple.sc.b s0, s1, s2 4205# CHECK-INSTR: cv.cmple.sc.b s0, s1, s2 4206# CHECK-ENCODING: [0x7b,0xd4,0x24,0x2d] 4207# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4208 4209//===----------------------------------------------------------------------===// 4210// cv.cmple.sci.h 4211//===----------------------------------------------------------------------===// 4212 4213cv.cmple.sci.h t0, t1, 0 4214# CHECK-INSTR: cv.cmple.sci.h t0, t1, 0 4215# CHECK-ENCODING: [0xfb,0x62,0x03,0x2c] 4216# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4217 4218cv.cmple.sci.h t3, t4, -32 4219# CHECK-INSTR: cv.cmple.sci.h t3, t4, -32 4220# CHECK-ENCODING: [0x7b,0xee,0x0e,0x2d] 4221# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4222 4223cv.cmple.sci.h a0, a1, 7 4224# CHECK-INSTR: cv.cmple.sci.h a0, a1, 7 4225# CHECK-ENCODING: [0x7b,0xe5,0x35,0x2e] 4226# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4227 4228cv.cmple.sci.h s0, s1, -1 4229# CHECK-INSTR: cv.cmple.sci.h s0, s1, -1 4230# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x2f] 4231# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4232 4233//===----------------------------------------------------------------------===// 4234// cv.cmple.sci.b 4235//===----------------------------------------------------------------------===// 4236 4237cv.cmple.sci.b t0, t1, 0 4238# CHECK-INSTR: cv.cmple.sci.b t0, t1, 0 4239# CHECK-ENCODING: [0xfb,0x72,0x03,0x2c] 4240# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4241 4242cv.cmple.sci.b t3, t4, -32 4243# CHECK-INSTR: cv.cmple.sci.b t3, t4, -32 4244# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x2d] 4245# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4246 4247cv.cmple.sci.b a0, a1, 7 4248# CHECK-INSTR: cv.cmple.sci.b a0, a1, 7 4249# CHECK-ENCODING: [0x7b,0xf5,0x35,0x2e] 4250# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4251 4252cv.cmple.sci.b s0, s1, -1 4253# CHECK-INSTR: cv.cmple.sci.b s0, s1, -1 4254# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x2f] 4255# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4256 4257//===----------------------------------------------------------------------===// 4258// cv.cmpgtu.h 4259//===----------------------------------------------------------------------===// 4260 4261cv.cmpgtu.h t0, t1, t2 4262# CHECK-INSTR: cv.cmpgtu.h t0, t1, t2 4263# CHECK-ENCODING: [0xfb,0x02,0x73,0x34] 4264# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4265 4266cv.cmpgtu.h t3, t4, t5 4267# CHECK-INSTR: cv.cmpgtu.h t3, t4, t5 4268# CHECK-ENCODING: [0x7b,0x8e,0xee,0x35] 4269# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4270 4271cv.cmpgtu.h a0, a1, a2 4272# CHECK-INSTR: cv.cmpgtu.h a0, a1, a2 4273# CHECK-ENCODING: [0x7b,0x85,0xc5,0x34] 4274# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4275 4276cv.cmpgtu.h s0, s1, s2 4277# CHECK-INSTR: cv.cmpgtu.h s0, s1, s2 4278# CHECK-ENCODING: [0x7b,0x84,0x24,0x35] 4279# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4280 4281//===----------------------------------------------------------------------===// 4282// cv.cmpgtu.b 4283//===----------------------------------------------------------------------===// 4284 4285cv.cmpgtu.b t0, t1, t2 4286# CHECK-INSTR: cv.cmpgtu.b t0, t1, t2 4287# CHECK-ENCODING: [0xfb,0x12,0x73,0x34] 4288# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4289 4290cv.cmpgtu.b t3, t4, t5 4291# CHECK-INSTR: cv.cmpgtu.b t3, t4, t5 4292# CHECK-ENCODING: [0x7b,0x9e,0xee,0x35] 4293# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4294 4295cv.cmpgtu.b a0, a1, a2 4296# CHECK-INSTR: cv.cmpgtu.b a0, a1, a2 4297# CHECK-ENCODING: [0x7b,0x95,0xc5,0x34] 4298# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4299 4300cv.cmpgtu.b s0, s1, s2 4301# CHECK-INSTR: cv.cmpgtu.b s0, s1, s2 4302# CHECK-ENCODING: [0x7b,0x94,0x24,0x35] 4303# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4304 4305//===----------------------------------------------------------------------===// 4306// cv.cmpgtu.sc.h 4307//===----------------------------------------------------------------------===// 4308 4309cv.cmpgtu.sc.h t0, t1, t2 4310# CHECK-INSTR: cv.cmpgtu.sc.h t0, t1, t2 4311# CHECK-ENCODING: [0xfb,0x42,0x73,0x34] 4312# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4313 4314cv.cmpgtu.sc.h t3, t4, t5 4315# CHECK-INSTR: cv.cmpgtu.sc.h t3, t4, t5 4316# CHECK-ENCODING: [0x7b,0xce,0xee,0x35] 4317# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4318 4319cv.cmpgtu.sc.h a0, a1, a2 4320# CHECK-INSTR: cv.cmpgtu.sc.h a0, a1, a2 4321# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x34] 4322# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4323 4324cv.cmpgtu.sc.h s0, s1, s2 4325# CHECK-INSTR: cv.cmpgtu.sc.h s0, s1, s2 4326# CHECK-ENCODING: [0x7b,0xc4,0x24,0x35] 4327# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4328 4329//===----------------------------------------------------------------------===// 4330// cv.cmpgtu.sc.b 4331//===----------------------------------------------------------------------===// 4332 4333cv.cmpgtu.sc.b t0, t1, t2 4334# CHECK-INSTR: cv.cmpgtu.sc.b t0, t1, t2 4335# CHECK-ENCODING: [0xfb,0x52,0x73,0x34] 4336# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4337 4338cv.cmpgtu.sc.b t3, t4, t5 4339# CHECK-INSTR: cv.cmpgtu.sc.b t3, t4, t5 4340# CHECK-ENCODING: [0x7b,0xde,0xee,0x35] 4341# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4342 4343cv.cmpgtu.sc.b a0, a1, a2 4344# CHECK-INSTR: cv.cmpgtu.sc.b a0, a1, a2 4345# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x34] 4346# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4347 4348cv.cmpgtu.sc.b s0, s1, s2 4349# CHECK-INSTR: cv.cmpgtu.sc.b s0, s1, s2 4350# CHECK-ENCODING: [0x7b,0xd4,0x24,0x35] 4351# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4352 4353//===----------------------------------------------------------------------===// 4354// cv.cmpgtu.sci.h 4355//===----------------------------------------------------------------------===// 4356 4357cv.cmpgtu.sci.h t0, t1, 0 4358# CHECK-INSTR: cv.cmpgtu.sci.h t0, t1, 0 4359# CHECK-ENCODING: [0xfb,0x62,0x03,0x34] 4360# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4361 4362cv.cmpgtu.sci.h t3, t4, 32 4363# CHECK-INSTR: cv.cmpgtu.sci.h t3, t4, 32 4364# CHECK-ENCODING: [0x7b,0xee,0x0e,0x35] 4365# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4366 4367cv.cmpgtu.sci.h a0, a1, 7 4368# CHECK-INSTR: cv.cmpgtu.sci.h a0, a1, 7 4369# CHECK-ENCODING: [0x7b,0xe5,0x35,0x36] 4370# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4371 4372cv.cmpgtu.sci.h s0, s1, 63 4373# CHECK-INSTR: cv.cmpgtu.sci.h s0, s1, 63 4374# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x37] 4375# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4376 4377//===----------------------------------------------------------------------===// 4378// cv.cmpgtu.sci.b 4379//===----------------------------------------------------------------------===// 4380 4381cv.cmpgtu.sci.b t0, t1, 0 4382# CHECK-INSTR: cv.cmpgtu.sci.b t0, t1, 0 4383# CHECK-ENCODING: [0xfb,0x72,0x03,0x34] 4384# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4385 4386cv.cmpgtu.sci.b t3, t4, 32 4387# CHECK-INSTR: cv.cmpgtu.sci.b t3, t4, 32 4388# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x35] 4389# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4390 4391cv.cmpgtu.sci.b a0, a1, 7 4392# CHECK-INSTR: cv.cmpgtu.sci.b a0, a1, 7 4393# CHECK-ENCODING: [0x7b,0xf5,0x35,0x36] 4394# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4395 4396cv.cmpgtu.sci.b s0, s1, 63 4397# CHECK-INSTR: cv.cmpgtu.sci.b s0, s1, 63 4398# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x37] 4399# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4400 4401//===----------------------------------------------------------------------===// 4402// cv.cmpgeu.h 4403//===----------------------------------------------------------------------===// 4404 4405cv.cmpgeu.h t0, t1, t2 4406# CHECK-INSTR: cv.cmpgeu.h t0, t1, t2 4407# CHECK-ENCODING: [0xfb,0x02,0x73,0x3c] 4408# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4409 4410cv.cmpgeu.h t3, t4, t5 4411# CHECK-INSTR: cv.cmpgeu.h t3, t4, t5 4412# CHECK-ENCODING: [0x7b,0x8e,0xee,0x3d] 4413# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4414 4415cv.cmpgeu.h a0, a1, a2 4416# CHECK-INSTR: cv.cmpgeu.h a0, a1, a2 4417# CHECK-ENCODING: [0x7b,0x85,0xc5,0x3c] 4418# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4419 4420cv.cmpgeu.h s0, s1, s2 4421# CHECK-INSTR: cv.cmpgeu.h s0, s1, s2 4422# CHECK-ENCODING: [0x7b,0x84,0x24,0x3d] 4423# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4424 4425//===----------------------------------------------------------------------===// 4426// cv.cmpgeu.b 4427//===----------------------------------------------------------------------===// 4428 4429cv.cmpgeu.b t0, t1, t2 4430# CHECK-INSTR: cv.cmpgeu.b t0, t1, t2 4431# CHECK-ENCODING: [0xfb,0x12,0x73,0x3c] 4432# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4433 4434cv.cmpgeu.b t3, t4, t5 4435# CHECK-INSTR: cv.cmpgeu.b t3, t4, t5 4436# CHECK-ENCODING: [0x7b,0x9e,0xee,0x3d] 4437# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4438 4439cv.cmpgeu.b a0, a1, a2 4440# CHECK-INSTR: cv.cmpgeu.b a0, a1, a2 4441# CHECK-ENCODING: [0x7b,0x95,0xc5,0x3c] 4442# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4443 4444cv.cmpgeu.b s0, s1, s2 4445# CHECK-INSTR: cv.cmpgeu.b s0, s1, s2 4446# CHECK-ENCODING: [0x7b,0x94,0x24,0x3d] 4447# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4448 4449//===----------------------------------------------------------------------===// 4450// cv.cmpgeu.sc.h 4451//===----------------------------------------------------------------------===// 4452 4453cv.cmpgeu.sc.h t0, t1, t2 4454# CHECK-INSTR: cv.cmpgeu.sc.h t0, t1, t2 4455# CHECK-ENCODING: [0xfb,0x42,0x73,0x3c] 4456# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4457 4458cv.cmpgeu.sc.h t3, t4, t5 4459# CHECK-INSTR: cv.cmpgeu.sc.h t3, t4, t5 4460# CHECK-ENCODING: [0x7b,0xce,0xee,0x3d] 4461# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4462 4463cv.cmpgeu.sc.h a0, a1, a2 4464# CHECK-INSTR: cv.cmpgeu.sc.h a0, a1, a2 4465# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x3c] 4466# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4467 4468cv.cmpgeu.sc.h s0, s1, s2 4469# CHECK-INSTR: cv.cmpgeu.sc.h s0, s1, s2 4470# CHECK-ENCODING: [0x7b,0xc4,0x24,0x3d] 4471# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4472 4473//===----------------------------------------------------------------------===// 4474// cv.cmpgeu.sc.b 4475//===----------------------------------------------------------------------===// 4476 4477cv.cmpgeu.sc.b t0, t1, t2 4478# CHECK-INSTR: cv.cmpgeu.sc.b t0, t1, t2 4479# CHECK-ENCODING: [0xfb,0x52,0x73,0x3c] 4480# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4481 4482cv.cmpgeu.sc.b t3, t4, t5 4483# CHECK-INSTR: cv.cmpgeu.sc.b t3, t4, t5 4484# CHECK-ENCODING: [0x7b,0xde,0xee,0x3d] 4485# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4486 4487cv.cmpgeu.sc.b a0, a1, a2 4488# CHECK-INSTR: cv.cmpgeu.sc.b a0, a1, a2 4489# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x3c] 4490# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4491 4492cv.cmpgeu.sc.b s0, s1, s2 4493# CHECK-INSTR: cv.cmpgeu.sc.b s0, s1, s2 4494# CHECK-ENCODING: [0x7b,0xd4,0x24,0x3d] 4495# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4496 4497//===----------------------------------------------------------------------===// 4498// cv.cmpgeu.sci.h 4499//===----------------------------------------------------------------------===// 4500 4501cv.cmpgeu.sci.h t0, t1, 0 4502# CHECK-INSTR: cv.cmpgeu.sci.h t0, t1, 0 4503# CHECK-ENCODING: [0xfb,0x62,0x03,0x3c] 4504# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4505 4506cv.cmpgeu.sci.h t3, t4, 32 4507# CHECK-INSTR: cv.cmpgeu.sci.h t3, t4, 32 4508# CHECK-ENCODING: [0x7b,0xee,0x0e,0x3d] 4509# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4510 4511cv.cmpgeu.sci.h a0, a1, 7 4512# CHECK-INSTR: cv.cmpgeu.sci.h a0, a1, 7 4513# CHECK-ENCODING: [0x7b,0xe5,0x35,0x3e] 4514# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4515 4516cv.cmpgeu.sci.h s0, s1, 63 4517# CHECK-INSTR: cv.cmpgeu.sci.h s0, s1, 63 4518# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x3f] 4519# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4520 4521//===----------------------------------------------------------------------===// 4522// cv.cmpgeu.sci.b 4523//===----------------------------------------------------------------------===// 4524 4525cv.cmpgeu.sci.b t0, t1, 0 4526# CHECK-INSTR: cv.cmpgeu.sci.b t0, t1, 0 4527# CHECK-ENCODING: [0xfb,0x72,0x03,0x3c] 4528# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4529 4530cv.cmpgeu.sci.b t3, t4, 32 4531# CHECK-INSTR: cv.cmpgeu.sci.b t3, t4, 32 4532# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x3d] 4533# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4534 4535cv.cmpgeu.sci.b a0, a1, 7 4536# CHECK-INSTR: cv.cmpgeu.sci.b a0, a1, 7 4537# CHECK-ENCODING: [0x7b,0xf5,0x35,0x3e] 4538# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4539 4540cv.cmpgeu.sci.b s0, s1, 63 4541# CHECK-INSTR: cv.cmpgeu.sci.b s0, s1, 63 4542# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x3f] 4543# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4544 4545//===----------------------------------------------------------------------===// 4546// cv.cmpltu.h 4547//===----------------------------------------------------------------------===// 4548 4549cv.cmpltu.h t0, t1, t2 4550# CHECK-INSTR: cv.cmpltu.h t0, t1, t2 4551# CHECK-ENCODING: [0xfb,0x02,0x73,0x44] 4552# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4553 4554cv.cmpltu.h t3, t4, t5 4555# CHECK-INSTR: cv.cmpltu.h t3, t4, t5 4556# CHECK-ENCODING: [0x7b,0x8e,0xee,0x45] 4557# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4558 4559cv.cmpltu.h a0, a1, a2 4560# CHECK-INSTR: cv.cmpltu.h a0, a1, a2 4561# CHECK-ENCODING: [0x7b,0x85,0xc5,0x44] 4562# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4563 4564cv.cmpltu.h s0, s1, s2 4565# CHECK-INSTR: cv.cmpltu.h s0, s1, s2 4566# CHECK-ENCODING: [0x7b,0x84,0x24,0x45] 4567# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4568 4569//===----------------------------------------------------------------------===// 4570// cv.cmpltu.b 4571//===----------------------------------------------------------------------===// 4572 4573cv.cmpltu.b t0, t1, t2 4574# CHECK-INSTR: cv.cmpltu.b t0, t1, t2 4575# CHECK-ENCODING: [0xfb,0x12,0x73,0x44] 4576# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4577 4578cv.cmpltu.b t3, t4, t5 4579# CHECK-INSTR: cv.cmpltu.b t3, t4, t5 4580# CHECK-ENCODING: [0x7b,0x9e,0xee,0x45] 4581# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4582 4583cv.cmpltu.b a0, a1, a2 4584# CHECK-INSTR: cv.cmpltu.b a0, a1, a2 4585# CHECK-ENCODING: [0x7b,0x95,0xc5,0x44] 4586# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4587 4588cv.cmpltu.b s0, s1, s2 4589# CHECK-INSTR: cv.cmpltu.b s0, s1, s2 4590# CHECK-ENCODING: [0x7b,0x94,0x24,0x45] 4591# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4592 4593//===----------------------------------------------------------------------===// 4594// cv.cmpltu.sc.h 4595//===----------------------------------------------------------------------===// 4596 4597cv.cmpltu.sc.h t0, t1, t2 4598# CHECK-INSTR: cv.cmpltu.sc.h t0, t1, t2 4599# CHECK-ENCODING: [0xfb,0x42,0x73,0x44] 4600# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4601 4602cv.cmpltu.sc.h t3, t4, t5 4603# CHECK-INSTR: cv.cmpltu.sc.h t3, t4, t5 4604# CHECK-ENCODING: [0x7b,0xce,0xee,0x45] 4605# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4606 4607cv.cmpltu.sc.h a0, a1, a2 4608# CHECK-INSTR: cv.cmpltu.sc.h a0, a1, a2 4609# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x44] 4610# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4611 4612cv.cmpltu.sc.h s0, s1, s2 4613# CHECK-INSTR: cv.cmpltu.sc.h s0, s1, s2 4614# CHECK-ENCODING: [0x7b,0xc4,0x24,0x45] 4615# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4616 4617//===----------------------------------------------------------------------===// 4618// cv.cmpltu.sc.b 4619//===----------------------------------------------------------------------===// 4620 4621cv.cmpltu.sc.b t0, t1, t2 4622# CHECK-INSTR: cv.cmpltu.sc.b t0, t1, t2 4623# CHECK-ENCODING: [0xfb,0x52,0x73,0x44] 4624# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4625 4626cv.cmpltu.sc.b t3, t4, t5 4627# CHECK-INSTR: cv.cmpltu.sc.b t3, t4, t5 4628# CHECK-ENCODING: [0x7b,0xde,0xee,0x45] 4629# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4630 4631cv.cmpltu.sc.b a0, a1, a2 4632# CHECK-INSTR: cv.cmpltu.sc.b a0, a1, a2 4633# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x44] 4634# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4635 4636cv.cmpltu.sc.b s0, s1, s2 4637# CHECK-INSTR: cv.cmpltu.sc.b s0, s1, s2 4638# CHECK-ENCODING: [0x7b,0xd4,0x24,0x45] 4639# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4640 4641//===----------------------------------------------------------------------===// 4642// cv.cmpltu.sci.h 4643//===----------------------------------------------------------------------===// 4644 4645cv.cmpltu.sci.h t0, t1, 0 4646# CHECK-INSTR: cv.cmpltu.sci.h t0, t1, 0 4647# CHECK-ENCODING: [0xfb,0x62,0x03,0x44] 4648# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4649 4650cv.cmpltu.sci.h t3, t4, 32 4651# CHECK-INSTR: cv.cmpltu.sci.h t3, t4, 32 4652# CHECK-ENCODING: [0x7b,0xee,0x0e,0x45] 4653# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4654 4655cv.cmpltu.sci.h a0, a1, 7 4656# CHECK-INSTR: cv.cmpltu.sci.h a0, a1, 7 4657# CHECK-ENCODING: [0x7b,0xe5,0x35,0x46] 4658# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4659 4660cv.cmpltu.sci.h s0, s1, 63 4661# CHECK-INSTR: cv.cmpltu.sci.h s0, s1, 63 4662# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x47] 4663# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4664 4665//===----------------------------------------------------------------------===// 4666// cv.cmpltu.sci.b 4667//===----------------------------------------------------------------------===// 4668 4669cv.cmpltu.sci.b t0, t1, 0 4670# CHECK-INSTR: cv.cmpltu.sci.b t0, t1, 0 4671# CHECK-ENCODING: [0xfb,0x72,0x03,0x44] 4672# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4673 4674cv.cmpltu.sci.b t3, t4, 32 4675# CHECK-INSTR: cv.cmpltu.sci.b t3, t4, 32 4676# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x45] 4677# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4678 4679cv.cmpltu.sci.b a0, a1, 7 4680# CHECK-INSTR: cv.cmpltu.sci.b a0, a1, 7 4681# CHECK-ENCODING: [0x7b,0xf5,0x35,0x46] 4682# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4683 4684cv.cmpltu.sci.b s0, s1, 63 4685# CHECK-INSTR: cv.cmpltu.sci.b s0, s1, 63 4686# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x47] 4687# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4688 4689//===----------------------------------------------------------------------===// 4690// cv.cmpleu.h 4691//===----------------------------------------------------------------------===// 4692 4693cv.cmpleu.h t0, t1, t2 4694# CHECK-INSTR: cv.cmpleu.h t0, t1, t2 4695# CHECK-ENCODING: [0xfb,0x02,0x73,0x4c] 4696# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4697 4698cv.cmpleu.h t3, t4, t5 4699# CHECK-INSTR: cv.cmpleu.h t3, t4, t5 4700# CHECK-ENCODING: [0x7b,0x8e,0xee,0x4d] 4701# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4702 4703cv.cmpleu.h a0, a1, a2 4704# CHECK-INSTR: cv.cmpleu.h a0, a1, a2 4705# CHECK-ENCODING: [0x7b,0x85,0xc5,0x4c] 4706# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4707 4708cv.cmpleu.h s0, s1, s2 4709# CHECK-INSTR: cv.cmpleu.h s0, s1, s2 4710# CHECK-ENCODING: [0x7b,0x84,0x24,0x4d] 4711# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4712 4713//===----------------------------------------------------------------------===// 4714// cv.cmpleu.b 4715//===----------------------------------------------------------------------===// 4716 4717cv.cmpleu.b t0, t1, t2 4718# CHECK-INSTR: cv.cmpleu.b t0, t1, t2 4719# CHECK-ENCODING: [0xfb,0x12,0x73,0x4c] 4720# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4721 4722cv.cmpleu.b t3, t4, t5 4723# CHECK-INSTR: cv.cmpleu.b t3, t4, t5 4724# CHECK-ENCODING: [0x7b,0x9e,0xee,0x4d] 4725# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4726 4727cv.cmpleu.b a0, a1, a2 4728# CHECK-INSTR: cv.cmpleu.b a0, a1, a2 4729# CHECK-ENCODING: [0x7b,0x95,0xc5,0x4c] 4730# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4731 4732cv.cmpleu.b s0, s1, s2 4733# CHECK-INSTR: cv.cmpleu.b s0, s1, s2 4734# CHECK-ENCODING: [0x7b,0x94,0x24,0x4d] 4735# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4736 4737//===----------------------------------------------------------------------===// 4738// cv.cmpleu.sc.h 4739//===----------------------------------------------------------------------===// 4740 4741cv.cmpleu.sc.h t0, t1, t2 4742# CHECK-INSTR: cv.cmpleu.sc.h t0, t1, t2 4743# CHECK-ENCODING: [0xfb,0x42,0x73,0x4c] 4744# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4745 4746cv.cmpleu.sc.h t3, t4, t5 4747# CHECK-INSTR: cv.cmpleu.sc.h t3, t4, t5 4748# CHECK-ENCODING: [0x7b,0xce,0xee,0x4d] 4749# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4750 4751cv.cmpleu.sc.h a0, a1, a2 4752# CHECK-INSTR: cv.cmpleu.sc.h a0, a1, a2 4753# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x4c] 4754# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4755 4756cv.cmpleu.sc.h s0, s1, s2 4757# CHECK-INSTR: cv.cmpleu.sc.h s0, s1, s2 4758# CHECK-ENCODING: [0x7b,0xc4,0x24,0x4d] 4759# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4760 4761//===----------------------------------------------------------------------===// 4762// cv.cmpleu.sc.b 4763//===----------------------------------------------------------------------===// 4764 4765cv.cmpleu.sc.b t0, t1, t2 4766# CHECK-INSTR: cv.cmpleu.sc.b t0, t1, t2 4767# CHECK-ENCODING: [0xfb,0x52,0x73,0x4c] 4768# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4769 4770cv.cmpleu.sc.b t3, t4, t5 4771# CHECK-INSTR: cv.cmpleu.sc.b t3, t4, t5 4772# CHECK-ENCODING: [0x7b,0xde,0xee,0x4d] 4773# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4774 4775cv.cmpleu.sc.b a0, a1, a2 4776# CHECK-INSTR: cv.cmpleu.sc.b a0, a1, a2 4777# CHECK-ENCODING: [0x7b,0xd5,0xc5,0x4c] 4778# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4779 4780cv.cmpleu.sc.b s0, s1, s2 4781# CHECK-INSTR: cv.cmpleu.sc.b s0, s1, s2 4782# CHECK-ENCODING: [0x7b,0xd4,0x24,0x4d] 4783# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4784 4785//===----------------------------------------------------------------------===// 4786// cv.cmpleu.sci.h 4787//===----------------------------------------------------------------------===// 4788 4789cv.cmpleu.sci.h t0, t1, 0 4790# CHECK-INSTR: cv.cmpleu.sci.h t0, t1, 0 4791# CHECK-ENCODING: [0xfb,0x62,0x03,0x4c] 4792# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4793 4794cv.cmpleu.sci.h t3, t4, 32 4795# CHECK-INSTR: cv.cmpleu.sci.h t3, t4, 32 4796# CHECK-ENCODING: [0x7b,0xee,0x0e,0x4d] 4797# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4798 4799cv.cmpleu.sci.h a0, a1, 7 4800# CHECK-INSTR: cv.cmpleu.sci.h a0, a1, 7 4801# CHECK-ENCODING: [0x7b,0xe5,0x35,0x4e] 4802# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4803 4804cv.cmpleu.sci.h s0, s1, 63 4805# CHECK-INSTR: cv.cmpleu.sci.h s0, s1, 63 4806# CHECK-ENCODING: [0x7b,0xe4,0xf4,0x4f] 4807# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4808 4809//===----------------------------------------------------------------------===// 4810// cv.cmpleu.sci.b 4811//===----------------------------------------------------------------------===// 4812 4813cv.cmpleu.sci.b t0, t1, 0 4814# CHECK-INSTR: cv.cmpleu.sci.b t0, t1, 0 4815# CHECK-ENCODING: [0xfb,0x72,0x03,0x4c] 4816# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4817 4818cv.cmpleu.sci.b t3, t4, 32 4819# CHECK-INSTR: cv.cmpleu.sci.b t3, t4, 32 4820# CHECK-ENCODING: [0x7b,0xfe,0x0e,0x4d] 4821# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4822 4823cv.cmpleu.sci.b a0, a1, 7 4824# CHECK-INSTR: cv.cmpleu.sci.b a0, a1, 7 4825# CHECK-ENCODING: [0x7b,0xf5,0x35,0x4e] 4826# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4827 4828cv.cmpleu.sci.b s0, s1, 63 4829# CHECK-INSTR: cv.cmpleu.sci.b s0, s1, 63 4830# CHECK-ENCODING: [0x7b,0xf4,0xf4,0x4f] 4831# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4832 4833//===----------------------------------------------------------------------===// 4834// cv.cplxmul.r 4835//===----------------------------------------------------------------------===// 4836 4837cv.cplxmul.r t0, t1, t2 4838# CHECK-INSTR: cv.cplxmul.r t0, t1, t2 4839# CHECK-ENCODING: [0xfb,0x02,0x73,0x54] 4840# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4841 4842cv.cplxmul.r t3, t4, t5 4843# CHECK-INSTR: cv.cplxmul.r t3, t4, t5 4844# CHECK-ENCODING: [0x7b,0x8e,0xee,0x55] 4845# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4846 4847cv.cplxmul.r a0, a1, a2 4848# CHECK-INSTR: cv.cplxmul.r a0, a1, a2 4849# CHECK-ENCODING: [0x7b,0x85,0xc5,0x54] 4850# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4851 4852cv.cplxmul.r s0, s1, s2 4853# CHECK-INSTR: cv.cplxmul.r s0, s1, s2 4854# CHECK-ENCODING: [0x7b,0x84,0x24,0x55] 4855# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4856 4857//===----------------------------------------------------------------------===// 4858// cv.cplxmul.i 4859//===----------------------------------------------------------------------===// 4860 4861cv.cplxmul.i t0, t1, t2 4862# CHECK-INSTR: cv.cplxmul.i t0, t1, t2 4863# CHECK-ENCODING: [0xfb,0x02,0x73,0x56] 4864# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4865 4866cv.cplxmul.i t3, t4, t5 4867# CHECK-INSTR: cv.cplxmul.i t3, t4, t5 4868# CHECK-ENCODING: [0x7b,0x8e,0xee,0x57] 4869# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4870 4871cv.cplxmul.i a0, a1, a2 4872# CHECK-INSTR: cv.cplxmul.i a0, a1, a2 4873# CHECK-ENCODING: [0x7b,0x85,0xc5,0x56] 4874# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4875 4876cv.cplxmul.i s0, s1, s2 4877# CHECK-INSTR: cv.cplxmul.i s0, s1, s2 4878# CHECK-ENCODING: [0x7b,0x84,0x24,0x57] 4879# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4880 4881//===----------------------------------------------------------------------===// 4882// cv.cplxmul.r.div2 4883//===----------------------------------------------------------------------===// 4884 4885cv.cplxmul.r.div2 t0, t1, t2 4886# CHECK-INSTR: cv.cplxmul.r.div2 t0, t1, t2 4887# CHECK-ENCODING: [0xfb,0x22,0x73,0x54] 4888# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4889 4890cv.cplxmul.r.div2 t3, t4, t5 4891# CHECK-INSTR: cv.cplxmul.r.div2 t3, t4, t5 4892# CHECK-ENCODING: [0x7b,0xae,0xee,0x55] 4893# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4894 4895cv.cplxmul.r.div2 a0, a1, a2 4896# CHECK-INSTR: cv.cplxmul.r.div2 a0, a1, a2 4897# CHECK-ENCODING: [0x7b,0xa5,0xc5,0x54] 4898# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4899 4900cv.cplxmul.r.div2 s0, s1, s2 4901# CHECK-INSTR: cv.cplxmul.r.div2 s0, s1, s2 4902# CHECK-ENCODING: [0x7b,0xa4,0x24,0x55] 4903# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4904 4905//===----------------------------------------------------------------------===// 4906// cv.cplxmul.i.div2 4907//===----------------------------------------------------------------------===// 4908 4909cv.cplxmul.i.div2 t0, t1, t2 4910# CHECK-INSTR: cv.cplxmul.i.div2 t0, t1, t2 4911# CHECK-ENCODING: [0xfb,0x22,0x73,0x56] 4912# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4913 4914cv.cplxmul.i.div2 t3, t4, t5 4915# CHECK-INSTR: cv.cplxmul.i.div2 t3, t4, t5 4916# CHECK-ENCODING: [0x7b,0xae,0xee,0x57] 4917# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4918 4919cv.cplxmul.i.div2 a0, a1, a2 4920# CHECK-INSTR: cv.cplxmul.i.div2 a0, a1, a2 4921# CHECK-ENCODING: [0x7b,0xa5,0xc5,0x56] 4922# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4923 4924cv.cplxmul.i.div2 s0, s1, s2 4925# CHECK-INSTR: cv.cplxmul.i.div2 s0, s1, s2 4926# CHECK-ENCODING: [0x7b,0xa4,0x24,0x57] 4927# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4928 4929//===----------------------------------------------------------------------===// 4930// cv.cplxmul.r.div4 4931//===----------------------------------------------------------------------===// 4932 4933cv.cplxmul.r.div4 t0, t1, t2 4934# CHECK-INSTR: cv.cplxmul.r.div4 t0, t1, t2 4935# CHECK-ENCODING: [0xfb,0x42,0x73,0x54] 4936# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4937 4938cv.cplxmul.r.div4 t3, t4, t5 4939# CHECK-INSTR: cv.cplxmul.r.div4 t3, t4, t5 4940# CHECK-ENCODING: [0x7b,0xce,0xee,0x55] 4941# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4942 4943cv.cplxmul.r.div4 a0, a1, a2 4944# CHECK-INSTR: cv.cplxmul.r.div4 a0, a1, a2 4945# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x54] 4946# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4947 4948cv.cplxmul.r.div4 s0, s1, s2 4949# CHECK-INSTR: cv.cplxmul.r.div4 s0, s1, s2 4950# CHECK-ENCODING: [0x7b,0xc4,0x24,0x55] 4951# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4952 4953//===----------------------------------------------------------------------===// 4954// cv.cplxmul.i.div4 4955//===----------------------------------------------------------------------===// 4956 4957cv.cplxmul.i.div4 t0, t1, t2 4958# CHECK-INSTR: cv.cplxmul.i.div4 t0, t1, t2 4959# CHECK-ENCODING: [0xfb,0x42,0x73,0x56] 4960# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4961 4962cv.cplxmul.i.div4 t3, t4, t5 4963# CHECK-INSTR: cv.cplxmul.i.div4 t3, t4, t5 4964# CHECK-ENCODING: [0x7b,0xce,0xee,0x57] 4965# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4966 4967cv.cplxmul.i.div4 a0, a1, a2 4968# CHECK-INSTR: cv.cplxmul.i.div4 a0, a1, a2 4969# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x56] 4970# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4971 4972cv.cplxmul.i.div4 s0, s1, s2 4973# CHECK-INSTR: cv.cplxmul.i.div4 s0, s1, s2 4974# CHECK-ENCODING: [0x7b,0xc4,0x24,0x57] 4975# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4976 4977//===----------------------------------------------------------------------===// 4978// cv.cplxmul.r.div8 4979//===----------------------------------------------------------------------===// 4980 4981cv.cplxmul.r.div8 t0, t1, t2 4982# CHECK-INSTR: cv.cplxmul.r.div8 t0, t1, t2 4983# CHECK-ENCODING: [0xfb,0x62,0x73,0x54] 4984# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4985 4986cv.cplxmul.r.div8 t3, t4, t5 4987# CHECK-INSTR: cv.cplxmul.r.div8 t3, t4, t5 4988# CHECK-ENCODING: [0x7b,0xee,0xee,0x55] 4989# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4990 4991cv.cplxmul.r.div8 a0, a1, a2 4992# CHECK-INSTR: cv.cplxmul.r.div8 a0, a1, a2 4993# CHECK-ENCODING: [0x7b,0xe5,0xc5,0x54] 4994# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 4995 4996cv.cplxmul.r.div8 s0, s1, s2 4997# CHECK-INSTR: cv.cplxmul.r.div8 s0, s1, s2 4998# CHECK-ENCODING: [0x7b,0xe4,0x24,0x55] 4999# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5000 5001//===----------------------------------------------------------------------===// 5002// cv.cplxmul.i.div8 5003//===----------------------------------------------------------------------===// 5004 5005cv.cplxmul.i.div8 t0, t1, t2 5006# CHECK-INSTR: cv.cplxmul.i.div8 t0, t1, t2 5007# CHECK-ENCODING: [0xfb,0x62,0x73,0x56] 5008# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5009 5010cv.cplxmul.i.div8 t3, t4, t5 5011# CHECK-INSTR: cv.cplxmul.i.div8 t3, t4, t5 5012# CHECK-ENCODING: [0x7b,0xee,0xee,0x57] 5013# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5014 5015cv.cplxmul.i.div8 a0, a1, a2 5016# CHECK-INSTR: cv.cplxmul.i.div8 a0, a1, a2 5017# CHECK-ENCODING: [0x7b,0xe5,0xc5,0x56] 5018# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5019 5020cv.cplxmul.i.div8 s0, s1, s2 5021# CHECK-INSTR: cv.cplxmul.i.div8 s0, s1, s2 5022# CHECK-ENCODING: [0x7b,0xe4,0x24,0x57] 5023# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5024 5025//===----------------------------------------------------------------------===// 5026// cv.cplxconj 5027//===----------------------------------------------------------------------===// 5028 5029cv.cplxconj t0, t1 5030# CHECK-INSTR: cv.cplxconj t0, t1 5031# CHECK-ENCODING: [0xfb,0x02,0x03,0x5c] 5032# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5033 5034cv.cplxconj t3, t4 5035# CHECK-INSTR: cv.cplxconj t3, t4 5036# CHECK-ENCODING: [0x7b,0x8e,0x0e,0x5c] 5037# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5038 5039cv.cplxconj a0, a1 5040# CHECK-INSTR: cv.cplxconj a0, a1 5041# CHECK-ENCODING: [0x7b,0x85,0x05,0x5c] 5042# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5043 5044cv.cplxconj s0, s1 5045# CHECK-INSTR: cv.cplxconj s0, s1 5046# CHECK-ENCODING: [0x7b,0x84,0x04,0x5c] 5047# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5048 5049//===----------------------------------------------------------------------===// 5050// cv.subrotmj 5051//===----------------------------------------------------------------------===// 5052 5053cv.subrotmj t0, t1, t2 5054# CHECK-INSTR: cv.subrotmj t0, t1, t2 5055# CHECK-ENCODING: [0xfb,0x02,0x73,0x64] 5056# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5057 5058cv.subrotmj t3, t4, t5 5059# CHECK-INSTR: cv.subrotmj t3, t4, t5 5060# CHECK-ENCODING: [0x7b,0x8e,0xee,0x65] 5061# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5062 5063cv.subrotmj a0, a1, a2 5064# CHECK-INSTR: cv.subrotmj a0, a1, a2 5065# CHECK-ENCODING: [0x7b,0x85,0xc5,0x64] 5066# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5067 5068cv.subrotmj s0, s1, s2 5069# CHECK-INSTR: cv.subrotmj s0, s1, s2 5070# CHECK-ENCODING: [0x7b,0x84,0x24,0x65] 5071# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5072 5073//===----------------------------------------------------------------------===// 5074// cv.subrotmj.div2 5075//===----------------------------------------------------------------------===// 5076 5077cv.subrotmj.div2 t0, t1, t2 5078# CHECK-INSTR: cv.subrotmj.div2 t0, t1, t2 5079# CHECK-ENCODING: [0xfb,0x22,0x73,0x64] 5080# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5081 5082cv.subrotmj.div2 t3, t4, t5 5083# CHECK-INSTR: cv.subrotmj.div2 t3, t4, t5 5084# CHECK-ENCODING: [0x7b,0xae,0xee,0x65] 5085# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5086 5087cv.subrotmj.div2 a0, a1, a2 5088# CHECK-INSTR: cv.subrotmj.div2 a0, a1, a2 5089# CHECK-ENCODING: [0x7b,0xa5,0xc5,0x64] 5090# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5091 5092cv.subrotmj.div2 s0, s1, s2 5093# CHECK-INSTR: cv.subrotmj.div2 s0, s1, s2 5094# CHECK-ENCODING: [0x7b,0xa4,0x24,0x65] 5095# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5096 5097//===----------------------------------------------------------------------===// 5098// cv.subrotmj.div4 5099//===----------------------------------------------------------------------===// 5100 5101cv.subrotmj.div4 t0, t1, t2 5102# CHECK-INSTR: cv.subrotmj.div4 t0, t1, t2 5103# CHECK-ENCODING: [0xfb,0x42,0x73,0x64] 5104# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5105 5106cv.subrotmj.div4 t3, t4, t5 5107# CHECK-INSTR: cv.subrotmj.div4 t3, t4, t5 5108# CHECK-ENCODING: [0x7b,0xce,0xee,0x65] 5109# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5110 5111cv.subrotmj.div4 a0, a1, a2 5112# CHECK-INSTR: cv.subrotmj.div4 a0, a1, a2 5113# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x64] 5114# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5115 5116cv.subrotmj.div4 s0, s1, s2 5117# CHECK-INSTR: cv.subrotmj.div4 s0, s1, s2 5118# CHECK-ENCODING: [0x7b,0xc4,0x24,0x65] 5119# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5120 5121//===----------------------------------------------------------------------===// 5122// cv.subrotmj.div8 5123//===----------------------------------------------------------------------===// 5124 5125cv.subrotmj.div8 t0, t1, t2 5126# CHECK-INSTR: cv.subrotmj.div8 t0, t1, t2 5127# CHECK-ENCODING: [0xfb,0x62,0x73,0x64] 5128# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5129 5130cv.subrotmj.div8 t3, t4, t5 5131# CHECK-INSTR: cv.subrotmj.div8 t3, t4, t5 5132# CHECK-ENCODING: [0x7b,0xee,0xee,0x65] 5133# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5134 5135cv.subrotmj.div8 a0, a1, a2 5136# CHECK-INSTR: cv.subrotmj.div8 a0, a1, a2 5137# CHECK-ENCODING: [0x7b,0xe5,0xc5,0x64] 5138# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5139 5140cv.subrotmj.div8 s0, s1, s2 5141# CHECK-INSTR: cv.subrotmj.div8 s0, s1, s2 5142# CHECK-ENCODING: [0x7b,0xe4,0x24,0x65] 5143# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5144 5145//===----------------------------------------------------------------------===// 5146// cv.add.div2 5147//===----------------------------------------------------------------------===// 5148 5149cv.add.div2 t0, t1, t2 5150# CHECK-INSTR: cv.add.div2 t0, t1, t2 5151# CHECK-ENCODING: [0xfb,0x22,0x73,0x6c] 5152# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5153 5154cv.add.div2 t3, t4, t5 5155# CHECK-INSTR: cv.add.div2 t3, t4, t5 5156# CHECK-ENCODING: [0x7b,0xae,0xee,0x6d] 5157# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5158 5159cv.add.div2 a0, a1, a2 5160# CHECK-INSTR: cv.add.div2 a0, a1, a2 5161# CHECK-ENCODING: [0x7b,0xa5,0xc5,0x6c] 5162# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5163 5164cv.add.div2 s0, s1, s2 5165# CHECK-INSTR: cv.add.div2 s0, s1, s2 5166# CHECK-ENCODING: [0x7b,0xa4,0x24,0x6d] 5167# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5168 5169//===----------------------------------------------------------------------===// 5170// cv.add.div4 5171//===----------------------------------------------------------------------===// 5172 5173cv.add.div4 t0, t1, t2 5174# CHECK-INSTR: cv.add.div4 t0, t1, t2 5175# CHECK-ENCODING: [0xfb,0x42,0x73,0x6c] 5176# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5177 5178cv.add.div4 t3, t4, t5 5179# CHECK-INSTR: cv.add.div4 t3, t4, t5 5180# CHECK-ENCODING: [0x7b,0xce,0xee,0x6d] 5181# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5182 5183cv.add.div4 a0, a1, a2 5184# CHECK-INSTR: cv.add.div4 a0, a1, a2 5185# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x6c] 5186# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5187 5188cv.add.div4 s0, s1, s2 5189# CHECK-INSTR: cv.add.div4 s0, s1, s2 5190# CHECK-ENCODING: [0x7b,0xc4,0x24,0x6d] 5191# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5192 5193//===----------------------------------------------------------------------===// 5194// cv.add.div8 5195//===----------------------------------------------------------------------===// 5196 5197cv.add.div8 t0, t1, t2 5198# CHECK-INSTR: cv.add.div8 t0, t1, t2 5199# CHECK-ENCODING: [0xfb,0x62,0x73,0x6c] 5200# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5201 5202cv.add.div8 t3, t4, t5 5203# CHECK-INSTR: cv.add.div8 t3, t4, t5 5204# CHECK-ENCODING: [0x7b,0xee,0xee,0x6d] 5205# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5206 5207cv.add.div8 a0, a1, a2 5208# CHECK-INSTR: cv.add.div8 a0, a1, a2 5209# CHECK-ENCODING: [0x7b,0xe5,0xc5,0x6c] 5210# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5211 5212cv.add.div8 s0, s1, s2 5213# CHECK-INSTR: cv.add.div8 s0, s1, s2 5214# CHECK-ENCODING: [0x7b,0xe4,0x24,0x6d] 5215# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5216 5217//===----------------------------------------------------------------------===// 5218// cv.sub.div2 5219//===----------------------------------------------------------------------===// 5220 5221cv.sub.div2 t0, t1, t2 5222# CHECK-INSTR: cv.sub.div2 t0, t1, t2 5223# CHECK-ENCODING: [0xfb,0x22,0x73,0x74] 5224# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5225 5226cv.sub.div2 t3, t4, t5 5227# CHECK-INSTR: cv.sub.div2 t3, t4, t5 5228# CHECK-ENCODING: [0x7b,0xae,0xee,0x75] 5229# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5230 5231cv.sub.div2 a0, a1, a2 5232# CHECK-INSTR: cv.sub.div2 a0, a1, a2 5233# CHECK-ENCODING: [0x7b,0xa5,0xc5,0x74] 5234# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5235 5236cv.sub.div2 s0, s1, s2 5237# CHECK-INSTR: cv.sub.div2 s0, s1, s2 5238# CHECK-ENCODING: [0x7b,0xa4,0x24,0x75] 5239# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5240 5241//===----------------------------------------------------------------------===// 5242// cv.sub.div4 5243//===----------------------------------------------------------------------===// 5244 5245cv.sub.div4 t0, t1, t2 5246# CHECK-INSTR: cv.sub.div4 t0, t1, t2 5247# CHECK-ENCODING: [0xfb,0x42,0x73,0x74] 5248# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5249 5250cv.sub.div4 t3, t4, t5 5251# CHECK-INSTR: cv.sub.div4 t3, t4, t5 5252# CHECK-ENCODING: [0x7b,0xce,0xee,0x75] 5253# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5254 5255cv.sub.div4 a0, a1, a2 5256# CHECK-INSTR: cv.sub.div4 a0, a1, a2 5257# CHECK-ENCODING: [0x7b,0xc5,0xc5,0x74] 5258# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5259 5260cv.sub.div4 s0, s1, s2 5261# CHECK-INSTR: cv.sub.div4 s0, s1, s2 5262# CHECK-ENCODING: [0x7b,0xc4,0x24,0x75] 5263# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5264 5265//===----------------------------------------------------------------------===// 5266// cv.sub.div8 5267//===----------------------------------------------------------------------===// 5268 5269cv.sub.div8 t0, t1, t2 5270# CHECK-INSTR: cv.sub.div8 t0, t1, t2 5271# CHECK-ENCODING: [0xfb,0x62,0x73,0x74] 5272# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5273 5274cv.sub.div8 t3, t4, t5 5275# CHECK-INSTR: cv.sub.div8 t3, t4, t5 5276# CHECK-ENCODING: [0x7b,0xee,0xee,0x75] 5277# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5278 5279cv.sub.div8 a0, a1, a2 5280# CHECK-INSTR: cv.sub.div8 a0, a1, a2 5281# CHECK-ENCODING: [0x7b,0xe5,0xc5,0x74] 5282# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5283 5284cv.sub.div8 s0, s1, s2 5285# CHECK-INSTR: cv.sub.div8 s0, s1, s2 5286# CHECK-ENCODING: [0x7b,0xe4,0x24,0x75] 5287# CHECK-NO-EXT: instruction requires the following: 'XCVsimd' (CORE-V SIMD ALU){{$}} 5288 5289