1# RUN: llvm-mc -triple=riscv32 --mattr=+xcvmem -show-encoding %s \ 2# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR 3# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvmem < %s \ 4# RUN: | llvm-objdump --no-print-imm-hex --mattr=+xcvmem -M no-aliases -d -r - \ 5# RUN: | FileCheck --check-prefix=CHECK-INSTR %s 6# RUN: not llvm-mc -triple riscv32 %s 2>&1 \ 7# RUN: | FileCheck -check-prefix=CHECK-NO-EXT %s 8 9cv.lb t0, (t1), 0 10# CHECK-INSTR: cv.lb t0, (t1), 0 11# CHECK-ENCODING: [0x8b,0x02,0x03,0x00] 12# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 13 14cv.lb a0, (a1), 2047 15# CHECK-INSTR: cv.lb a0, (a1), 2047 16# CHECK-ENCODING: [0x0b,0x85,0xf5,0x7f] 17# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 18 19cv.lb t0, (t1), t2 20# CHECK-INSTR: cv.lb t0, (t1), t2 21# CHECK-ENCODING: [0xab,0x32,0x73,0x00] 22# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 23 24cv.lb a0, (a1), a2 25# CHECK-INSTR: cv.lb a0, (a1), a2 26# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x00] 27# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 28 29cv.lb t0, t2(t1) 30# CHECK-INSTR: cv.lb t0, t2(t1) 31# CHECK-ENCODING: [0xab,0x32,0x73,0x08] 32# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 33 34cv.lb a0, a2(a1) 35# CHECK-INSTR: cv.lb a0, a2(a1) 36# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x08] 37# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 38 39cv.lbu t0, (t1), 0 40# CHECK-INSTR: cv.lbu t0, (t1), 0 41# CHECK-ENCODING: [0x8b,0x42,0x03,0x00] 42# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 43 44cv.lbu a0, (a1), 2047 45# CHECK-INSTR: cv.lbu a0, (a1), 2047 46# CHECK-ENCODING: [0x0b,0xc5,0xf5,0x7f] 47# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 48 49cv.lbu t0, (t1), t2 50# CHECK-INSTR: cv.lbu t0, (t1), t2 51# CHECK-ENCODING: [0xab,0x32,0x73,0x10] 52# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 53 54cv.lbu a0, (a1), a2 55# CHECK-INSTR: cv.lbu a0, (a1), a2 56# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x10] 57# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 58 59cv.lbu t0, t2(t1) 60# CHECK-INSTR: cv.lbu t0, t2(t1) 61# CHECK-ENCODING: [0xab,0x32,0x73,0x18] 62# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 63 64cv.lbu a0, a2(a1) 65# CHECK-INSTR: cv.lbu a0, a2(a1) 66# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x18] 67# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 68 69cv.lh t0, (t1), 0 70# CHECK-INSTR: cv.lh t0, (t1), 0 71# CHECK-ENCODING: [0x8b,0x12,0x03,0x00] 72# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 73 74cv.lh a0, (a1), 2047 75# CHECK-INSTR: cv.lh a0, (a1), 2047 76# CHECK-ENCODING: [0x0b,0x95,0xf5,0x7f] 77# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 78 79cv.lh t0, (t1), t2 80# CHECK-INSTR: cv.lh t0, (t1), t2 81# CHECK-ENCODING: [0xab,0x32,0x73,0x02] 82# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 83 84cv.lh a0, (a1), a2 85# CHECK-INSTR: cv.lh a0, (a1), a2 86# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x02] 87# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 88 89cv.lh t0, t2(t1) 90# CHECK-INSTR: cv.lh t0, t2(t1) 91# CHECK-ENCODING: [0xab,0x32,0x73,0x0a] 92# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 93 94cv.lh a0, a2(a1) 95# CHECK-INSTR: cv.lh a0, a2(a1) 96# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x0a] 97# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 98 99cv.lhu t0, (t1), 0 100# CHECK-INSTR: cv.lhu t0, (t1), 0 101# CHECK-ENCODING: [0x8b,0x52,0x03,0x00] 102# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 103 104cv.lhu a0, (a1), 2047 105# CHECK-INSTR: cv.lhu a0, (a1), 2047 106# CHECK-ENCODING: [0x0b,0xd5,0xf5,0x7f] 107# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 108 109cv.lhu t0, (t1), t2 110# CHECK-INSTR: cv.lhu t0, (t1), t2 111# CHECK-ENCODING: [0xab,0x32,0x73,0x12] 112# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 113 114cv.lhu a0, (a1), a2 115# CHECK-INSTR: cv.lhu a0, (a1), a2 116# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x12] 117# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 118 119cv.lhu t0, t2(t1) 120# CHECK-INSTR: cv.lhu t0, t2(t1) 121# CHECK-ENCODING: [0xab,0x32,0x73,0x1a] 122# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 123 124cv.lhu a0, a2(a1) 125# CHECK-INSTR: cv.lhu a0, a2(a1) 126# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x1a] 127# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 128 129cv.lw t0, (t1), 0 130# CHECK-INSTR: cv.lw t0, (t1), 0 131# CHECK-ENCODING: [0x8b,0x22,0x03,0x00] 132# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 133 134cv.lw a0, (a1), 2047 135# CHECK-INSTR: cv.lw a0, (a1), 2047 136# CHECK-ENCODING: [0x0b,0xa5,0xf5,0x7f] 137# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 138 139cv.lw t0, (t1), t2 140# CHECK-INSTR: cv.lw t0, (t1), t2 141# CHECK-ENCODING: [0xab,0x32,0x73,0x04] 142# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 143 144cv.lw a0, (a1), a2 145# CHECK-INSTR: cv.lw a0, (a1), a2 146# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x04] 147# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 148 149cv.lw t0, t2(t1) 150# CHECK-INSTR: cv.lw t0, t2(t1) 151# CHECK-ENCODING: [0xab,0x32,0x73,0x0c] 152# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 153 154cv.lw a0, a2(a1) 155# CHECK-INSTR: cv.lw a0, a2(a1) 156# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x0c] 157# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 158 159cv.sb t0, (t1), 0 160# CHECK-INSTR: cv.sb t0, (t1), 0 161# CHECK-ENCODING: [0x2b,0x00,0x53,0x00] 162# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 163 164cv.sb a0, (a1), 2047 165# CHECK-INSTR: cv.sb a0, (a1), 2047 166# CHECK-ENCODING: [0xab,0x8f,0xa5,0x7e] 167# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 168 169cv.sb t0, (t1), t2 170# CHECK-INSTR: cv.sb t0, (t1), t2 171# CHECK-ENCODING: [0xab,0x33,0x53,0x20] 172# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 173 174cv.sb a0, (a1), a2 175# CHECK-INSTR: cv.sb a0, (a1), a2 176# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x20] 177# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 178 179cv.sb t0, t2(t1) 180# CHECK-INSTR: cv.sb t0, t2(t1) 181# CHECK-ENCODING: [0xab,0x33,0x53,0x28] 182# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 183 184cv.sb a0, a2(a1) 185# CHECK-INSTR: cv.sb a0, a2(a1) 186# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x28] 187# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 188 189cv.sh t0, (t1), 0 190# CHECK-INSTR: cv.sh t0, (t1), 0 191# CHECK-ENCODING: [0x2b,0x10,0x53,0x00] 192# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 193 194cv.sh a0, (a1), 2047 195# CHECK-INSTR: cv.sh a0, (a1), 2047 196# CHECK-ENCODING: [0xab,0x9f,0xa5,0x7e] 197# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 198 199cv.sh t0, (t1), t2 200# CHECK-INSTR: cv.sh t0, (t1), t2 201# CHECK-ENCODING: [0xab,0x33,0x53,0x22] 202# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 203 204cv.sh a0, (a1), a2 205# CHECK-INSTR: cv.sh a0, (a1), a2 206# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x22] 207# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 208 209cv.sh t0, t2(t1) 210# CHECK-INSTR: cv.sh t0, t2(t1) 211# CHECK-ENCODING: [0xab,0x33,0x53,0x2a] 212# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 213 214cv.sh a0, a2(a1) 215# CHECK-INSTR: cv.sh a0, a2(a1) 216# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x2a] 217# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 218 219cv.sw t0, (t1), 0 220# CHECK-INSTR: cv.sw t0, (t1), 0 221# CHECK-ENCODING: [0x2b,0x20,0x53,0x00] 222# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 223 224cv.sw a0, (a1), 2047 225# CHECK-INSTR: cv.sw a0, (a1), 2047 226# CHECK-ENCODING: [0xab,0xaf,0xa5,0x7e] 227# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 228 229cv.sw t0, (t1), t2 230# CHECK-INSTR: cv.sw t0, (t1), t2 231# CHECK-ENCODING: [0xab,0x33,0x53,0x24] 232# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 233 234cv.sw a0, (a1), a2 235# CHECK-INSTR: cv.sw a0, (a1), a2 236# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x24] 237# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 238 239cv.sw t0, t2(t1) 240# CHECK-INSTR: cv.sw t0, t2(t1) 241# CHECK-ENCODING: [0xab,0x33,0x53,0x2c] 242# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 243 244cv.sw a0, a2(a1) 245# CHECK-INSTR: cv.sw a0, a2(a1) 246# CHECK-ENCODING: [0x2b,0xb6,0xa5,0x2c] 247# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} 248