xref: /llvm-project/llvm/test/MC/Hexagon/smallcore_dis.s (revision 252c42354eca54274ed7b10c32c73c6937478e8b) 
1# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump --no-print-imm-hex -d - | FileCheck %s
2# RUN: llvm-mc -triple=hexagon -mcpu=hexagonv67t -filetype=obj %s | llvm-objdump --no-print-imm-hex --mcpu=hexagonv67t -d - | FileCheck %s
3
4    .text
5{
6  r1 = memb(r0)
7  if (p0) memb(r0) = r2
8}
9
10# CHECK:      { r1 = memb(r0+#0)
11# CHECK-NEXT:   if (p0) memb(r0+#0) = r2 }
12