xref: /llvm-project/llvm/test/MC/Disassembler/RISCV/branch-targets.txt (revision ad923edfc1ce0c0b60e8270954c8d098aab3c3f8)
1# RUN: llvm-mc -assemble -triple riscv32 -mattr=+c -filetype=obj %s -o - 2>&1 | \
2# RUN:   llvm-objdump -d --mattr=+c -M no-aliases - | FileCheck %s
3# RUN: llvm-mc -assemble -triple riscv64 -mattr=+c -filetype=obj %s -o - 2>&1 | \
4# RUN:   llvm-objdump -d --mattr=+c -M no-aliases - | FileCheck %s
5
6label1:
7.option norvc
8  j label1
9  j label2
10  bnez a0, label1
11  bnez a0, label2
12.option rvc
13  j label1
14  j label2
15  bnez a0, label1
16  bnez a0, label2
17# CHECK-LABEL: <label1>:
18# CHECK-NEXT: jal zero, 0x0 <label1>
19# CHECK-NEXT: jal zero, 0x18 <label2>
20# CHECK-NEXT: bne a0, zero, 0x0 <label1>
21# CHECK-NEXT: bne a0, zero, 0x18 <label2>
22# CHECK-NEXT: c.j 0x0 <label1>
23# CHECK-NEXT: c.j 0x18 <label2>
24# CHECK-NEXT: c.bnez a0, 0x0 <label1>
25# CHECK-NEXT: c.bnez a0, 0x18 <label2>
26
27label2:
28