1# RUN: llvm-mc -triple=arc -disassemble %s | FileCheck %s 2 3# CHECK: ld %r0, [%r0,0] 40x00 0x10 0x00 0x00 5 6# CHECK: ldh %r0, [%r0,0] 70x00 0x10 0x00 0x01 8 9# CHECK: ldb %r0, [%r0,0] 100x00 0x10 0x80 0x00 11 12# CHECK: ld %r1, [%r0,12] 130x0c 0x10 0x01 0x00 14 15# CHECK: ld %r14, [%fp,-12] 160xf4 0x13 0x0e 0xb0 17 18# CHECK: ld %r3, [%r0,-12] 190xf4 0x10 0x03 0x80 20 21# CHECK: ld %r0, [%r0,244] 220xf4 0x10 0x00 0x00 23 24# CHECK: ld %r0, [%r0,-12] 250xf4 0x10 0x00 0x80 26 27# CHECK: ldh.x %r3, [%r1,0] 280x00 0x11 0x43 0x01 29 30# CHECK: ldh.x %r2, [%r1,2] 310x02 0x11 0x42 0x01 32 33# CHECK: ldh.x %r2, [%fp,-132] 340x7c 0x13 0x42 0xb1 35 36# CHECK: ld %r0, [%r0,64000] 370x30 0x20 0x80 0x0f 0x00 0x00 0x00 0xfa 38 39# CHECK: ld %r6, [63920] 400x00 0x16 0x06 0x70 0x00 0x00 0xb0 0xf9 41 42# CHECK: stb %r2, [%sp,35] 430x23 0x1c 0x82 0x30 44 45# CHECK: st %r7, [63920] 460x00 0x1e 0xc0 0x71 0x00 0x00 0xb0 0xf9 47 48# CHECK: ldb.ab %r1, [%r0,1] 490x01 0x10 0x81 0x04 50 51# CHECK: stb.ab %r2, [%r0,1] 520x01 0x18 0x92 0x00 53 54# CHECK: ldh.ab %r3, [%r0,12] 550x0C 0x10 0x03 0x05 56 57# CHECK: sth.ab %r4, [%r0,18] 580x12 0x18 0x14 0x01 59 60# CHECK: ld.ab %r5, [%r2,128] 610x80 0x12 0x05 0x04 62 63# CHECK: st.ab %r6, [%r2,64] 640x40 0x1A 0x90 0x01 65 66# CHECK: ldb.aw %r7, [%r0,1] 670x01 0x10 0x87 0x02 68 69# CHECK: stb.aw %r8, [%r0,1] 700x01 0x18 0x0A 0x02 71 72# CHECK: ldh.aw %r3, [%r0,12] 730x0C 0x10 0x03 0x03 74 75# CHECK: sth.aw %r3, [%r0,18] 760x12 0x18 0xCC 0x00 77 78# CHECK: ld.aw %r6, [%r2,128] 790x80 0x12 0x06 0x02 80 81# CHECK: st.aw %r6, [%r2,64] 820x40 0x1A 0x88 0x01 83 84# CHECK: ld.aw %r6, [%r2,128] 850x80 0x12 0x06 0x02 86 87# CHECK: st.aw %r6, [%r2,64] 880x40 0x1A 0x88 0x01 89 90# CHECK: ldb.x.di.aw %r0, [%r8,8] 910x08 0x10 0xC0 0x1A 92 93# CHECK: stb.di.ab %r0, [%r9,64] 940x40 0x19 0x32 0x10 95 96# LR instructions with a U6 immediate bit pattern 97# ([33] maps to the [%count0] auxilary register) 98 99# CHECK: lr %r0, [33] 1000x6a 0x20 0x40 0x08 101 102# CHECK: lr %r7, [33] 1030x6a 0x27 0x40 0x08 104 105# CHECK: lr %r15, [33] 1060x6a 0x27 0x40 0x18 107 108# CHECK: lr %r22, [33] 1090x6a 0x26 0x40 0x28 110 111# LR instructions with an S12 immediate bit pattern 112 113# CHECK: lr %r0, [33] 1140xaa 0x20 0x40 0x08 115 116# The following don't necessarily map to real auxilary registers, but 117# the different range of numbers helps exercise the S12 decoder. 118 119# CHECK: lr %r0, [-33] 1200xaa 0x20 0x60 0x08 121 122# CHECK: lr %r0, [97] 1230xaa 0x20 0x41 0x08 124 125# CHECK: lr %r0, [-97] 1260xaa 0x20 0x61 0x08 127