1// +the required for RCWSMASK_EL1, RCWMASK_EL1 2// +el2vmsa required for TTBR0_EL2 (VSCTLR_EL2), VTTBR_EL2 3// +vh required for TTBR1_EL2 4 5// RUN: not llvm-mc -triple aarch64 -mattr=+d128,+the,+el2vmsa,+vh -show-encoding %s -o - 2> %t | FileCheck %s 6// RUN: FileCheck %s --input-file=%t --check-prefix=ERRORS 7 8// RUN: not llvm-mc -triple aarch64 -mattr=+the,+el2vmsa,+vh -show-encoding %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128 9 10 msrr TTBR0_EL1, x0, x1 11// CHECK: msrr TTBR0_EL1, x0, x1 // encoding: [0x00,0x20,0x58,0xd5] 12// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 13 msrr TTBR1_EL1, x0, x1 14// CHECK: msrr TTBR1_EL1, x0, x1 // encoding: [0x20,0x20,0x58,0xd5] 15// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 16 msrr PAR_EL1, x0, x1 17// CHECK: msrr PAR_EL1, x0, x1 // encoding: [0x00,0x74,0x58,0xd5] 18// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 19 msrr RCWSMASK_EL1, x0, x1 20// CHECK: msrr RCWSMASK_EL1, x0, x1 // encoding: [0x60,0xd0,0x58,0xd5] 21// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 22 msrr RCWMASK_EL1, x0, x1 23// CHECK: msrr RCWMASK_EL1, x0, x1 // encoding: [0xc0,0xd0,0x58,0xd5] 24// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 25 msrr TTBR0_EL2, x0, x1 26// CHECK: msrr TTBR0_EL2, x0, x1 // encoding: [0x00,0x20,0x5c,0xd5] 27// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 28 msrr TTBR1_EL2, x0, x1 29// CHECK: msrr TTBR1_EL2, x0, x1 // encoding: [0x20,0x20,0x5c,0xd5] 30// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 31 msrr VTTBR_EL2, x0, x1 32// CHECK: msrr VTTBR_EL2, x0, x1 // encoding: [0x00,0x21,0x5c,0xd5] 33// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 34 35 msrr VTTBR_EL2, x0, x1 36// CHECK: msrr VTTBR_EL2, x0, x1 // encoding: [0x00,0x21,0x5c,0xd5] 37// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 38 msrr VTTBR_EL2, x2, x3 39// CHECK: msrr VTTBR_EL2, x2, x3 // encoding: [0x02,0x21,0x5c,0xd5] 40// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 41 msrr VTTBR_EL2, x4, x5 42// CHECK: msrr VTTBR_EL2, x4, x5 // encoding: [0x04,0x21,0x5c,0xd5] 43// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 44 msrr VTTBR_EL2, x6, x7 45// CHECK: msrr VTTBR_EL2, x6, x7 // encoding: [0x06,0x21,0x5c,0xd5] 46// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 47 msrr VTTBR_EL2, x8, x9 48// CHECK: msrr VTTBR_EL2, x8, x9 // encoding: [0x08,0x21,0x5c,0xd5] 49// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 50 msrr VTTBR_EL2, x10, x11 51// CHECK: msrr VTTBR_EL2, x10, x11 // encoding: [0x0a,0x21,0x5c,0xd5] 52// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 53 msrr VTTBR_EL2, x12, x13 54// CHECK: msrr VTTBR_EL2, x12, x13 // encoding: [0x0c,0x21,0x5c,0xd5] 55// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 56 msrr VTTBR_EL2, x14, x15 57// CHECK: msrr VTTBR_EL2, x14, x15 // encoding: [0x0e,0x21,0x5c,0xd5] 58// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 59 msrr VTTBR_EL2, x16, x17 60// CHECK: msrr VTTBR_EL2, x16, x17 // encoding: [0x10,0x21,0x5c,0xd5] 61// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 62 msrr VTTBR_EL2, x18, x19 63// CHECK: msrr VTTBR_EL2, x18, x19 // encoding: [0x12,0x21,0x5c,0xd5] 64// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 65 msrr VTTBR_EL2, x20, x21 66// CHECK: msrr VTTBR_EL2, x20, x21 // encoding: [0x14,0x21,0x5c,0xd5] 67// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 68 msrr VTTBR_EL2, x22, x23 69// CHECK: msrr VTTBR_EL2, x22, x23 // encoding: [0x16,0x21,0x5c,0xd5] 70// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 71 msrr VTTBR_EL2, x24, x25 72// CHECK: msrr VTTBR_EL2, x24, x25 // encoding: [0x18,0x21,0x5c,0xd5] 73// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 74 msrr VTTBR_EL2, x26, x27 75// CHECK: msrr VTTBR_EL2, x26, x27 // encoding: [0x1a,0x21,0x5c,0xd5] 76// ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128 77 78 msrr TTBR0_EL1, x0, x2 79// ERRORS: error: expected second odd register of a consecutive same-size even/odd register pair 80 81 msrr TTBR0_EL1, x0 82// ERRORS: error: expected comma 83 84 msrr TTBR0_EL1, x1, x2 85// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair 86 87 msrr TTBR0_EL1, x31, x0 88// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair 89 90 msrr TTBR0_EL1, xzr, x30 91// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair 92 93 msrr TTBR0_EL1, xzr 94// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair 95 96 msrr S3_0_c2_c0_1 97// ERRORS: error: too few operands for instruction 98 99 msrr x0, x1, S3_0_c2_c0_1 100// ERRORS: error: expected first even register of a consecutive same-size even/odd register pair 101