1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s 2 3// --------------------------------------------------------------------------// 4// Invalid predicate register 5 6st1q {z0.q}, p8, [z0.d, x0] 7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) 8// CHECK-NEXT: st1q {z0.q}, p8, [z0.d, x0] 9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 10 11st1q {z23.q}, p2/m, [z3.d] 12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 13// CHECK-NEXT: st1q {z23.q}, p2/m, [z3.d] 14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 15 16st1q {z21.q}, p2.q, [z5.d] 17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) 18// CHECK-NEXT: st1q {z21.q}, p2.q, [z5.d] 19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 20 21// --------------------------------------------------------------------------// 22// Invalid order of base & offset 23 24st1q {z0.q}, p0, [x0, z0.d] 25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 26// CHECK-NEXT: st1q {z0.q}, p0, [x0, z0.d] 27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 28 29// --------------------------------------------------------------------------// 30// Invalid general purpose register 31 32st1q {z0.q}, p0, [z0.d, sp] 33// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 34// CHECK-NEXT: st1q {z0.q}, p0, [z0.d, sp] 35// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 36 37// --------------------------------------------------------------------------// 38// Invalid suffixes 39 40st1q {z0.q}, p0, [z2.s] 41// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 42// CHECK-NEXT: st1q {z0.q}, p0, [z2.s] 43// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 44