1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s 2 3// --------------------------------------------------------------------------// 4// Invalid vector lane index 5 6bfmlslt z0.s, z0.h, z0.h[8] 7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. 8// CHECK-NEXT: bfmlslt z0.s, z0.h, z0.h[8] 9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 10 11bfmlslt z0.s, z0.h, z0.h[-1] 12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7]. 13// CHECK-NEXT: bfmlslt z0.s, z0.h, z0.h[-1] 14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 15 16bfmlslt z0.s, z0.h, z8.h[2] 17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction 18// CHECK-NEXT: bfmlslt z0.s, z0.h, z8.h[2] 19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 20 21// --------------------------------------------------------------------------// 22// Invalid vector suffix 23 24bfmlslt z0.s, z0.s, z0.s[0] 25// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 26// CHECK-NEXT: bfmlslt z0.s, z0.s, z0.s[0] 27// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 28 29bfmlslt z23.d, z23.h, z13.h 30// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 31// CHECK-NEXT: bfmlslt z23.d, z23.h, z13.h 32// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 33 34bfmlslt z23.d, z23.h, z13.h[1] 35// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width 36// CHECK-NEXT: bfmlslt z23.d, z23.h, z13.h[1] 37// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: 38