xref: /llvm-project/llvm/test/MC/AArch64/SVE2p1/addqv-diagnostics.s (revision 835de8dcf1021de6d224625558346fd127358e08) 
1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
2
3// --------------------------------------------------------------------------//
4// Invalid predicate register
5
6addqv v0.2d, p11, z0.d
7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
8// CHECK-NEXT: addqv v0.2d, p11, z0.d
9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10
11// --------------------------------------------------------------------------//
12// Invalid vector register
13
14addqv v0.4h, p1, z0.h
15// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
16// CHECK-NEXT: addqv v0.4h, p1, z0.h
17// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18
19addqv z1.s, p1, z0.s
20// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
21// CHECK-NEXT: addqv z1.s, p1, z0.s
22// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23
24// --------------------------------------------------------------------------//
25// Invalid vector suffix
26
27addqv v0.8h, p1, z0.s
28// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
29// CHECK-NEXT: addqv v0.8h, p1, z0.s
30// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
31